职位描述：
Job responsibility
Responsible for IC backend design,including floorplan, place&route, clock tree insertion, scan insertion,physical verification, timing closure, power analysis and tapeout.
Job requirement
Candidate should be familiar with the IC backend flow, from RTL/netlist to GDS, including tools such as Synopsys Astro or Cadence FE/LEC, Mentor Calibre, and Magma, also familiar with the design file types such as LEF, DEF, SDF, and GDS.
Perl or TCL script writing skill is a requirement
Involved in at least 1 successful foundry tapeout
Experience of mix signal layout is preferred
Experience of DFT design, synthesis and STA are preferred
Experience of Magma flow is preferred
Qualification:
Requirements include a BS/MS in Electrical Engineering, excellent English language skills - oral and writing, proven interpersonal, group communication skills, detail oriented and a good team-worker. Experience working with multinational company is a plus.
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