美国奥加中国研发机构校园宣讲会

标 题: 美国奥加中国研发机构校园宣讲会
发信站: 水木社区 (Fri Dec 15 16:30:13 2006), 站内

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美国奥加(AGEIA)科技股份有限公司（中国）招聘

AGEIA公司是世界领先的芯片公司，致力于交互式现实技术研究，研发应用于该领域的新一代向量计算并行处理加速器和相关解决方案，具有雄厚的投资规模。拥有世界上领先的PhysX产品：专用物理模拟处理器（PPU），这代表一种全新技术使虚拟世界可以与交互式的现实世界相媲美。

为适应中国研发中心发展需求，公司计划招聘优秀工程师和部门经理职位。所有的职位都提供绝对有竞争力的薪金待遇和发展机会。

同时也欢迎优秀的应届研究生、博士生应聘相关职位

AGEIATMTechnologies Inc. is a fabless semiconductor company dedicated to delivering pervasive interactive reality to next-generation 3D games. Its flagship product, the PhysXTM chip, is leading dedicated Physics Processing Unit (PPU) - a completely new hardware category that bridges the gap between virtual worlds in game and responsive physical reality. The PhysX chip allows developers to use active physics-based environments for a more life-like entertainment experience.

We invite smart, experienced and aggressive members of R&D on board. All positions provide very competitive salary, benefits and wealth creation opportunity.

电子邮件： hiring@

公司网站： ww***com[点击查看]


工作地点：北京。
我们会通过电话及Email方式及时通知合格候选人参加面试

其他职位详情,请查询jo***.cn[点击查看],并请注明申请职位名称







Campus Activity Calendar

学校
日期
时间
地点
北京工业大学
20-Dec-06
10:00
第二实验楼1407
北京大学
21-Dec-06
14:00
理科二号楼2129室
中国科学科院研究生院
21-Dec-06
19:00
中关村教学楼S-106室
清华大学
10-Jan-07
10:00
待定
其他安排将持续更新，敬请关注。

此次校园招聘，将本着认真对待每一位职位申请者的原则，我们将现场收取简历并由我们的部门经理进行人工简历筛选

Part of JD
AGEIA Position Specification

Position: Senior IC Physical Design Engineer
PRIMARY RESPONSIBILITY: Key member of the Hardware Engineering team who will be working on floorplanning, timing closure and optimization and physical verification.

DESCRIPTION: We are looking for a self-motivated, team-oriented senior IC physical design engineer. This person will be working with a team to deliver complex physics processing ASICs using leading-edge digital silicon technology. Responsibilities include working on high-speed ASICs from conceptual studies to silicon. Ability to analyze a design for power, timing, area and yield and refining the development methodology to support high performance power optimized solution is required. The applicant should have proven successful tape-out experience of complex ASICs. The applicant should be able to demonstrate a deep understanding of deep sub-micron effects and their impact on a chosen design methodology.


REQUIRED KNOWLEDGE & EDUCATION:
University degree in Electrical Engineering, Computer Engineering or equivalent industry experience
5 years ASIC development or related experience
3+ years of direct layout experience in a leading technical position
Demonstrated experience in:
1.Solid understanding of physical design flows and tools
2.High performance designs in 130 nm or below
3.Understanding of power management and power optimizations
4.Understanding of design for yield
5.Detailed understanding of timing closure challenges (OCV, SI, skew) and related tools (timing driven placement, clock planning, timing analysis, statistical timing, extraction, SI-Crosstalk analyis)
6.Experience with formal verification (Verplex)
7.Experience with Primetime
8.Scripting (Scheme/tcl/shell/Perl)
9.Strong experience with either Magma, Cadence, Synopsys Flow
10.Mentor Graphics Calibre (LVS, DRC, and RVE)
11.Experience with Cadence Virtuoso is a plus
12.Working knowledge with Unix/Linux OS
Leadership skills
Proven ability to meet deadlines/successful completion of deliverables
Established track record of working on complex SOCs
Ability to communicate and work well with other departments
Ability to work under pressure
Analytical, thorough, resourceful and detail-oriented
Self-motivated, hardworking, flexible
Experience working with distributed teams is plus

AGEIA Position Specification

Position: Senior Verification Lead

PRIMARY RESPONSIBILITY: Key member of the Hardware Engineering team who will be responsible for leading a team of ASIC/SOC verification in our Beijing office.

DESCRIPTION: We are looking for a self-motivated, team-oriented senior ASIC/SOC verification team leader. This person will be working with a team to deliver complex physics processing ASICs using leading-edge silicon technology. Responsibilities include working on high-speed ASICs from specification to silicon, and assisting in ASIC bring-up. Ability to code-up test-benches specialized for unit-level testing, multi-unit testing and full chip testing in Verilog or SystemVerilog is required. The applicant should have proven successful tape-out experience of complex ASICs. In addition to testing the applicant should be able to demonstrate identification of verification metrics as well as to implement support for verification metric tracking. Diligence in tracking down open issues to closure required.

REQUIRED KNOWLEDGE & EDUCATION:
University degree in Electrical Engineering, Computer Engineering or equivalent industry experience
5 years ASIC development or related experience
3+ years of direct verification experience in a leading technical position
Demonstrated experience in:
13.Solid understanding in testbench design and implementation
14.Verilog experience is a must
15.High performance designs in 130 nm or below
16.Understanding of verification metrics and coverage
17.Understanding of formal verification approaches is a plus
18.Scripting (Perl/shell) and makefiles
19.SystemVerilog is a strong plus
20.C-programming is a strong plus
21.Multi-core processor architecture is plus
Excellent communication skills, both written and verbal
Leadership skills
Proven ability to meet deadlines/successful completion of deliverables
Established track record of delivering complex SOC verification projects
Ability to communicate and work well with other departments
Ability to work under pressure
Analytical, thorough, resourceful and detail-oriented
Self-motivated, hardworking, flexible
Experience working with distributed teams is plus

AGEIA Position Specification
Position: Director of Silicon Engineering


PRIMARY RESPONSIBILITY: Key member of the Hardware Engineering team who will be responsible for hiring a team of professionals VLSI engineers, as well as managing and directing the design activities in our Beijing office.

DESCRIPTION: The primary role of the Director of ASIC Engineering will be to ensure the proficient execution of the ASIC/SOC implementation activities in the Beijing VLSI Engineering group of AGEIA, while ensuring the effective and efficient use of development personnel. In this position, the incumbent will lead a team of leads, developers, and support personnel. You will also be responsible for collaborating closely with our Architectural team, System Engineering, Software Engineering, Product Engineering.?You will be responsible for not only the development of new products but also required to manage sustaining engineering for shipping products as required.

REQUIRED KNOWLEDGE & EDUCATION:
University degree in Electrical Engineering, Computer Engineering or equivalent industry experience
8 years ASIC development or related experience
5+ years of direct management experience
Demonstrated experience in:
Multi-core processor architecture is plus
High performance designs in 130 nm or below
Design for power efficiency
COT Flow
Understanding of full custom design flow
Integrating of 3rd party IP
Design for manufacturability and reliability
Excellent communication skills, both?written and verbal
Exceptional leadership/people management skills
Proven ability to meet deadlines/successful completion of deliverables
Established track record of delivering complex SOC designs into production at least in 130nm
Strong internal relationship management skills
Ability to communicate and work well with other departments
Excellent time management skills
Ability to work under pressure
Analytical, thorough, resourceful and detail-oriented
Self-motivated, hardworking, flexible
Experience working with distributed teams


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