Cadence PV Intern Wanted

Cadence PV Intern Wanted
发信站: 饮水思源 (2006年12月24日11:08:03 星期天)

Position: PV(Product Validation) Engineer Intern in Shanghai 
Requirement :
-->The candidate should have basic knowledge of HDL(Verilog preferred) and mic
roelectronics. Knowledge of IC DESIGN flow is highly preferable. 
-->Previous experience of ASIC design (Cadence/Synopsys/Magma platforms) is hi
ghly preferable. 
-->Candidate must possess good Chinese and English communication skills. 
-->Candidate must have demonstrated strong problem solving skills, ability to 
work on large software systems. Highly motivated and passion to work is requir
ed. Detail focusing, performance oriented. Major in EE/CS, and all level of ex
periences are welcomed. MS is preferred.  
Job Descirption:
1. Validate EDA software in ASIC design flow. 
2. Responsible for developing, applying, and maintaining quality standards for
 complex EDA software system. 
3. Develops and executes EDA software test plans. 
4. Analyzes and writes test standards and procedures. 
5. In charge of Customer Acceptance Test.  

Notice :
-->For those candidates who are highly interested in this position, please sen
d you resume(C and E) by attachment to aaronsshao@
-->Those candidates who are in your 2nd year of post-graduate life(研二) is pr
eferred.
-->Cause the requirement of the position, we need a guarantee of at least 4 da
ys/per week from you.