思科系统硬件工程师招聘

思科系统硬件工程师招聘
发信站: 饮水思源 (2006年12月30日19:29:39 星期六)

Note: 
-	The job description below is for Senior ASIC/FPGA Design Engineers

Job Title: Hardware Engineer (ASIC/FPGA Design Engineer)

Job Description
-	Fully define an FPGA/ASIC design based on high-level functional requirements

-	Document and review top-level and block architectures
-	Implement blocks in Verilog RTL
-	Synthesize and close timing on the design
-	Work closely with Design Verification team to review strategy, testplans and
 assist with debugs
-	Work on code-coverage analysis, top-level connections, etc.
-	For FPGA designs, perform back-end placement and routing
-	Assist in lab bring-up, using logic-analyzer tools
-	Adherence to process and sound methodology

Skills Required
-	2+ years experience in FPGA and/or ASIC logic design
-	Ability to translate high-level functions into block designs
-	Outstanding coding and scripting skills (Verilog, C, Perl)
-	Demonstrated knowledge in FPGA/ASIC physical aspects (placement, routing, PL
L, I/O, memories, etc.)
-	Experience with industry tools for synthesis, timing analysis 
-	Outstanding written and spoken communication skills
-	Experience in mentoring junior designers
-	Well organized and Process oriented
-	Knowledge of Ethernet is a plus

Educational Background
Requires MSEE/CS combined with 2+ years of related 

Job Title:  Hardware Engineer (ASIC/FPGA Design Verification Engineer)

Job Description:
Participate in architecture and design verification of complex networking ASIC
.  Responsibilities include:
-	Architecture/Micro-Architecture definition
-	Standalone and Integrated functional verification; 
-	Documentation and review of Verification architecture and testplans
-	Develop verification environment (models, checkers, packet manager) using Sp
ecman/Vera
-	Develop random, pseudo-random and directed tests
-	Establish verification effectiveness using assertion/functional/code coverag
e and code reviews
-	RTL and gates simulation, debug and root cause
-	Regression triage and debug
-	Formal verification and equivalence checking.
-	Lab debug and design validation

Skills required:
-	Prior significant verification experience on complex ASICs.  
-	Good background in networking concepts.  
-	Experience with Vera/Specman and Verilog.  
-	Chip and system and test experience.  
-	Programming and scripting skills.
-	Good planning skills (well partioned designs, well organized code)
-	Outstanding written and verbal communication skills
-	Capability of critical thinking, challenging design intent

Education:
MSEE with 2+ yrs relevant experience 

有意应聘者，请将简历发至amli2@。