职位描述：
Responsibility:
The engineer should be in charge of verilog coding, micro-architecture design and level simulation.
He or she should be able to use ASIC tools and FPGA tools to complete the design task.
In order to verify the whole design in FPGA system, the designer will synthesize and then P&R the design with FPGA tools.
If necessary, designer will cooperate with team member to solve bug in system level.
What is more, the candidate is required to use the logic analyzer and oscillator to debug in FPGA.
Requirement:
A BS/MS in Electrical Engineering (or equivalent).
Experience with verilog code is necessary. Moreover, the knowledge about simulation and synthesis tools is a plus.
FPGA and/or CPLD design experience is plus.
The designer should be team-player.
The candidate should be self-motivated and be able to work under pressure
The successful candidate is expected to have a strong technical background in digital circuit design.
Fluency in English and Mandarin.
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