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Synopsys公司(Nasdaq:性SNPS)是为全球集成电路设计提供电子设计自动化(EDA)软件工 具的主导企业。为全球电子市场提供先进的IC设计与验证平台,致力于复杂的芯片上系统 (SoCs)的开发。同时,Synopsys公司还提供知识产权和设计服务,为客户简化设计过程, 提高产品上市速度。Synopsys公司总部设在美国加州Mountain View,有超过60家分公司分 布在北美、欧洲、日本与亚洲。 Position: R&D Engineer Location: Shanghai Job Responsibilities: Responsible for designing, developing, troubleshooting and debugging software programs for the leading EDA verification technology for Verilog. Will be invo lved in all phases of software development, including project planning, proble m identification, design specifications, development, scheduling, implementati on and testing. This job requires the ability to analyze and specify solutions for complex software design problems. Job Requirements: Must have BS in CS/EE with 5+ years of relevant experience or MS with 0+ years of experience in programming software for operating systems, compiler technol ogies,utilizing machine assembly and/or job control languages, and working kno wledge of software capabilities. The individual should have experience on deve lopment of complex software projects, familiarity with C/C++ coding, and a str ong background in data structures and algorithms. It is essential that the ind ividual has strong desires to learn and explore new technologies and are able to demonstrate good analysis and problem solving skills. Prior knowledge and e xperience of CAD tool development are required. If you are interested in this position, please send your resume (both in chine se and english) to: zongweil@