- 工作地点：北京
- 职位：招90nm工艺后端设计实习生
- 信息来源：新水木BBS
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发信站: 水木社区 (Tue Mar 20 09:05:04 2007), 站内
JOB Requirements: BSEE or MSEE working experience in IC physical design.
Must be efficient in the following skills:
1) Timing analysis using synopsys primetime tool and timing closure
2) Formal verification with synopsys formality or similar tool
3) Place and route tool with Blast-fusion or Astro
4) DFT concepts of SCAN and BIST
5) Programming skills using Perl or Tcl is required
JOB Description: Responsibility includes floorplanning, place and route, static timing analysis, physical verification (DRC/LVS).
Contact Info:
======================================
Rachel Xie
C2 Microsystems Inc.(Beijing),IC Team
Tel: 86-10-51721188 Ext-223
FAX: 86-10-51721319
Email: rxie@
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