Cadence PV Intern wanted

Cadence PV Intern wanted
发信站: 饮水思源 (2007年04月17日09:49:25 星期二)

We want :
- MS in EE/CS
- Solid experience in working on digital simulation tools preferably with some
digital design background.
- Good software skills including scripting skills like Shell, Perl, awk, tcl/t
ck, or some other programming exposure.
- 2 or more years related experience with digital design and simulation flow u
sing Cadence, Synopsys, Mentor or other EDA tools as an user or a support pers
on, product validation(QA) engineer or software developer.
- Verilog and VHDL expertise is a big plus.
You will :
- Plan and develop the strategy to test EDA software for digital simulator, di
gital signal and digital design environment.
- Develop detailed procedures to test, debug, troubleshoot and ensure the soft
ware is performing up to the specifications provided by analog designers and u
phold the software quality standards.
- Develop scripts used for testing in regression in Perl, Shell and C.
- Create digital designs for testing the coded software.
- Communicate and closely work with a team of professionals in R&D, Product En
gineering, and software release teams.

-----> You can learn too many advanced design methodologies in this team
-----> Working at least 4 days a week
-----> Those candidate who can contribute a long term internship is preferred

-----> Please send your resumes(English & Chinese) to aarons@ if 

       you're interested.