代友发帖招兼职英译汉专利翻译，长期有活

标 题: 【代友发帖】招兼职英译汉专利翻译，长期有活
发信站: 水木社区 (Thu May 17 20:18:14 2007), 站内

【代友发帖】招兼职英译汉专利翻译，长期有活


要求：
1.理工科背景，计算机、电子、通信、机电专业的优先；
2.熟悉科技英语，最好对专利文献有认识，有相关领域翻译经验；
3.守信用，能够为客户保密、准时交稿；
4.有充裕的时间能够翻译，并保证一定的翻译质量；
5.能接受210 words的试译（试译内容见下）；
6.每次交稿48小时内即付稿酬（需要对译稿进行初步校对，主要是防止漏译、严重错译）；
7.稿酬不高，50-60元/K英文单词；如果合作顺利，可逐渐提高稿酬标准，并且长期有活合作；
8.请将个人简历、试译译稿、联系方式（最好是手机）、翻译经历之类的详细信息发送到信箱：

patent_corp@，遴选之后，会直接与合适人选电话联系；
9.欢迎高校同学尝试。



【注意】：代友发文，不要回本人站内信箱，也勿咨询本人，谢谢！




Part.I
METHOD FOR FABRICATING 1T-DRAM ON BULK SILICON

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional
Application No. 60/782,479, filed on March 15, 2006. The disclosure of the
above application is incorporated herein by reference in its entirety.
FIELD
[0002] The present disclosure relates to memory arrays and, more
particularly, to memory arrays fabricated on bulk silicon.

Part.II
1. An integrated circuit comprising:
a bulk technology integrated circuit (bulk IC) including a bulk silicon
layer and complementary MOSFET (CMOS) transistors fabricated thereon; and
a first single transistor dynamic random access memory (1T
DRAM) cell arranged adjacent to and integrated with said bulk IC.
2. The integrated circuit of claim 1 wherein said first 1T DRAM cell
includes:
an amorphous silicon layer; and
first and second gates including first and second gate oxide layers
arranged adjacent to said amorphous silicon layer and first and second gate
polysilicon layers arranged in said first and second gate oxide layers.

Part.III

ABSTRACT OF THE DISCLOSURE
An integrated circuit includes a bulk technology integrated circuit (bulk IC)
including a bulk silicon layer and complementary MOSFET (CMOS) transistors
fabricated thereon. The integrated circuit also includes a single transistor
dynamic random access memory (1T DRAM) cell arranged adjacent to and
integrated with the bulk IC.





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