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Responsibilities:
-Use mainstream EDA tools and advanced methodology to do IC physical layer design.
-Implement 65nm advanced process IC P&R and Timing complete solution.
-Use C Shell/Perl/Tcl to automate design flow.
Requirements:
-major in microelectronics or relative department.
-Have the experience of using Cadence, Synopsys or Magma backend tools.
-Familiar with Script programming, having physical synthesis, SI experience as a plus.
-Good communication and positive attitude.