招IC设计人员及EDA软件开发人员

标 题: 招IC设计人员及EDA软件开发人员
发信站: 水木社区 (Wed Jul 25 17:03:50 2007), 站内

Company Introduction:
Agate Logic is a global pioneer of the innovative configurable system-on-chip (SoC) technologies. The company offers a full spectrum of SoC devices, software design tools, intellectual property (IP), and design services.

Agate Logic is headquartered in U.S.A., and is currently hiring engineering and field support talents in its new Beijing R&D center.
　　
Agate Logic 致力于可配置系统芯片的开发与销售，采用本土化的芯片制造商，目标定位于多种应用类市场领域，例如通信设备、工业控制系统、消费类电子产品等。我们的产品以可配置、可编程、多功能为特点，提供了一个通用的设计平台，可以运用于任何领域。我们的通用芯片平台，高效的EDA软件加上可配置的IP模块，能为系统提供商带来更多的便利。

Agate Logic是全球领先的CSoC芯片设计公司，公司总部位于美国加州，由几位留美博士共同创立，已有超过五年的历史。现在致力于发展中国的业务，推动中国本土芯片产业的发展，分别在北京和上海设立了研发和销售中心。Agate Logic北京研发中心现位于中关村科技园区清华科技园内。

Agate Logic在北京成立的研发中心是我们的一项重要战略，吸纳优秀的软件和硬件技术人才是确保我公司保持健康成长的关键。我们迫切需要拥有各类技术的优秀工程师加盟我公司。

地址：北京海淀区清华大学清华科技园
E-mail: hr@

Job Titles：
Software Department 软件部
- C++ Software Engineer C++软件工程师 (2 positions)
- Software Build & Release Engineer 软件发布工程师 (1 position)
- Technical Writer 技术文档工程师（1 position）
- Senior EDA Back-end Software Engineers 资深EDA后端软件工程师 (2 positions)
- EDA Back-end (Algorithm) Software Engineer EDA后端（算法）软件工程师 (3 positions)

IC Design Department 集成电路部
- IC Front-end Design Engineer IC前端设计工程师 (1 position)
- Senior IC Front-end Design Engineer 资深IC前端设计工程师 (1 position)
- Senior Verification Engineer 资深验证工程师 (1 position)
- Verification Engineer 验证工程师 (1 position)
- Senior IC Back-end Layout Engineer 资深IC后端设计工程师 (1 position)
- Senior IC Circuit Designer 资深IC电路设计工程师 (1 position)
- Product Engineering Manager 产品经理 （1 position）

Sales & Marketing Department 市场拓展部
- Sales Account Manager 销售客户经理 （1 position）

Job Title: C++ Software Engineer C++软件工程师 (2 positions)
Job Responsibilities:
With help from senior staff, specify, design and implement software components as part of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- M.S., or B.S. with 2 years of experience in related areas;
- Have at least 1 year of experience in software development with talents in graphical user interface design;
- Familiar with MFC;
- Excellent programming skills in object-oriented design, C++.
Preferences:
- Familiar with Microsoft Windows Programming;
- Familiar with Qt;
- Familiar with Linux, GCC;
- Skillful in shell scripts, Python, and/or TCL.
职位职责：
协助高级工程师，进行可配置片上系统解决方案EDA软件的设计，定义，开发。或负责对某一模块的设计开发。
职位要求：
- 大学本科以上学历，有2年相关工作经验，电子工程或者计算机相关专业
- 至少有1年用户界面开发经验，熟悉Qt或者MFC
- 良好的C++编程能力，对面向对象的设计思想有深入的理解
- 熟悉Linux，GCC者优先
- 有数字电路设计经验者优先

Job Title: Software Build & Release Engineer 软件发布工程师 (1 position)
Job Responsibilities:
- Setup and maintain the software development environment for version control, build, debug, regression test, and product release.
- Help define and execute large-scale performance evaluation experiments on networks of computers.
Requirements:
- MS or BS with at least 2 years of experience;
- Excellent written and verbal communication skills;
- Skillful in C, C++, shell scripts, Python, and/or Perl.
- Experience with Windows and Linux;
Preferences:
- Good knowledge of EDA design flow.
- Skillful in using GNU compiler tool chains including gcc and make, and various scripting languages, such as csh, bash, python, and perl.
职位职责：
建立和维护软件开发环境，对软件产品进行编译、整合、发布。包括版本控制，编译，调试，回归测试 和产品发布。协助设计、执行网络式的大规模性能评估试验。
职位要求：
- 大学本科以上学历，有2年工作经验
- 熟练使用MSVC2005，GNU Make进行软件的编译
- 熟练使用C，C++，Shell脚本，Python，TCL
- 有使用Windows及 Linux相关经验
- 熟悉EDA设计流程者优先

Job Title: Technical Writer 技术文档工程师（1 position）
Job Responsibilities:
Write, edit, format, and illustrate both online and printed documentation, including product data sheets, application notes, and software user guides.
Requirements:
- BS or higher degree major in English for Science or Electronic related specialty with at least 1 year technical writing or related experience;
–Excellent written and verbal communications skills in Chinese and English.
–Detail-oriented and highly-organized.
–Work with hardware and software engineers to create and update contents.
–Able to understand and explain highly technical subject matter.
–Familiarity with Microsoft Word, and popular drawing software.
Preferences:
- Additional experience in these areas is beneficial: Photoshop, Illustrator, FrontPage, Notes, Microsoft Project, CSS, Knowledge/Content Management, HTML, XML.
职位职责：
协助软件工程师，进行专业技术文档的撰写，整理和管理，包括产品数据手册，应用指南，用户指南等。
职位要求：
- 科技英语或者电子技术相关专业本科以上学历
- 优秀的中英文书写及口语能力，要求具有专业英语八级水平
- 文笔清晰，概括能力强，逻辑严密，条理性强，能很好地理解并解释高科技事物
- 熟练使用Microsoft office和常用的绘图工具，如Photoshop，Illustrator等
- 有较强的沟通能力
- 有电子工程或计算机背景，或有相关文档经验的优先

Job Title: Senior EDA Back-end Software Engineer
资深EDA后端软件工程师 (2 positions)
Job Responsibilities:
Independently specify, design, implement and test software components as part of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- Ph.D., M.S. with at least 3 years of experiences, or B.S. with 5 years of experiences in related areas;
- At least 2 plus years of experiences in EDA software development with solid understanding in at least one area of EDA algorithms;
- Excellent strong programming skills in object-oriented design, C++;
- Good team player with communication and management skills.
Preferences:
- Knowledge of algorithms used in RTL/logic synthesis, technology mapping, placement, routing, timing models and analysis, and/or FPGA architectures.
- Familiar with shell scripts, Python, Perl and/or Tcl.
职位职责：
独立地完成EDA设计工具的描述、设计、实现与测试等相关工作，提供完整的可配置片上系统解决方案。
职位要求：
- 大学硕士以上学历，三年相关工作经验；或者本科学历，有5年相关工作经验
- 至少有2年以上EDA软件开发经验，
- C++编程能力强
- 有团队精神，语言沟通能力强，有一定管理能力
- 了解RTL/Logic综合，技术映射，布局布线，时序分析及FPGA架构者优先

Job Title: EDA Back-end (Algorithm) Software Engineer
EDA后端（算法）软件工程师 (3 positions)
Job Responsibilities:
With help from senior staff, specify, design, implement and test software components as part of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- M.S., or B.S. with 2 years of experience in related areas;
- At least 2 plus years of experience in software development with talents in algorithm design;
- Excellent strong programming skills in object-oriented design, C++;
- Good team player with communication skill.
Preferences:
- Experience with algorithms used in RTL/logic synthesis, technology mapping, placement, routing, timing models and analysis, and/or FPGA architectures;
- Related courses or work in design automation for digital systems;
- Familiar with shell scripts, Python, Perl and/or Tcl.
职位职责：
协助完成EDA设计工具的描述、设计、实现与测试等相关工作，提供完整的可配置片上系统解决方案。
职位要求：
- 大学本科以上学历，2年以上算法设计相关工作经验
- C++编程能力强
- 熟悉RTL/Logic综合，技术映射，布局布线，时序分析及FPGA架构者优先
- 有相关数字系统设计自动化经验者优先

Job Title: IC Front-end Design Engineer IC前端设计工程师 (1 position)
Job Responsibilities:
Independently design, verify re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- B.S. with at least 2 years’ working experience, or M.S. with 1 years’ project experience in logic design.
- Good knowledge on Verilog/VHDL.
- Familiar with logic synthesis, simulation and verification tools, such as DC, Modelsim/VCS.
- Good programming skills in script language, such as TCL, perl.
- Good documentation and communication skill, in both Chinese and English
Preferences:
- Familiar with Static Timing Analysis using PrimeTime.
- Skillful in shell scripts, Python, and/or Perl.
职位职责：
独立地对ASIC 或 FPGA的优化硬件可重用HDL模型进行描述，设计，执行，并验证
职位要求：
- 大学本科以上学历，有2年工作经验；或者硕士学历，有1年逻辑设计项目经验
- 熟悉Verilog/VHDL，熟练使用逻辑综合，仿真和验证工具，如DC, Modelsim/VCS
符合以下条件者优先考虑：
- 较好的脚本语言编程能力，如TCL, perl.
- 能够熟练使用PrimeTime 做静态时序分析，精通Shell脚本，Python，Perl

Job Title: Senior IC Front-end Design Engineer 资深IC前端设计工程师 (1 position)
Job Responsibilities:
Independently specify, design, implement, verify hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- M.S. with at least 2 years of experience, or B.S. with 4 years’ experience in processor, memory controller, PCI, or networking equipment design;
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools;
- Familiar with Front-end Flow, logic synthesis using Synopsys Design Compiler, timing check with PrimeTime, test bench development and verification and design-for-test scan insertion;
- Have a track record of successful achievement in complex design projects;
- Good programming skills in script language, such as tcl, perl.
- Good documentation and communication skill, in both Chinese and English.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Skillful in C, C++, shell scripts, Python, and/or Perl.
职位职责：
独立地对ASIC 或 FPGA的优化硬件可重用HDL模型进行描述，设计，执行，并验证
职位要求：
- 硕士学历2年以上工作经验；或者本科学历，有4年以上在处理器，内存控制其，PCI，或网络相关芯片设计等方面工作经验
- Verilog，VHDL设计经验丰富，熟练使用逻辑综合，仿真和验证工具
- 熟悉前端设计流程，熟练使用Synopsys Design Compiler, PrimeTime
- 有很强的脚本语言编程能力，如TCL, perl
- 优秀的中英文交流及文档书写能力
- 熟悉FPGA者优先

Job Title: Senior Verification Engineer 资深验证工程师 (1 position)
Job Responsibilities:
Independently specify, design complex SoC verification platform to verify complex SoC.
Requirements:
- M.S. in E.E. with more than 3 years’ complex SoC verification experience;
- Hands on HDL RTL coding, and assertion-based verification methods;
- Familiar with and related EDA verification tools (such as VCS +Vera, Questasim) ;
- Familiar with C, system-verilog language;
- Good documentation and communication skill,in both Chinese and English.
Preferences:
- Familiar with script languages such as csh, tcl or perl
- Familiar with FPGA
职位职责：
独立地设计复杂的片上系统验证平台
职位要求：
- E.E．硕士学历，3年以上复杂片上系统验证经验
- 熟悉RTL级HDL编码及验证方法
- 熟练使用相关EDA验证工具，如VCS +Vera, Questasim等
- 熟悉C, System-Verilog 语言
- 优秀的中英文交流及文档书写能力

Job Title: Verification Engineer 验证工程师 (1 position)
Job Responsibilities:
To do the complex SoC function verification and gate-level netlist verification.
Requirements:
- Bachelor in E.E. with 2 to 3 years project experience or Master in E.E. with 1 to 2 years’s SoC verification experience;
- Hands on HDL RTL coding, familiar with Assertion-based verification language;
- Familiar with and related EDA verification tools.
Preferences:
- Familiar with script languages such as csh, tcl or perl
- Familiar with C, System-Verilog language
- Familiar with FPGA
职位职责：
负责复杂片上系统功能及门级网表验证
职位要求：
- E.E学士学位，2到3年相关工作经验；或E.E硕士学位，1到2年片上系统验证经验。
- 熟悉RTL级HDL编码及验证语言
- 熟悉相关EDA验证工具
- 熟悉csh, tcl 或 perl等脚本语言，C, System-Verilog 语言，FPGA者优先

Job Title: IC Back-end Layout Engineer IC后端设计工程师 (1 position)
Job Responsibilities:
- Responsible for developing and verifying complex digital designs with an emphasis on backend tasks of automated and manual placement and timing closure.
- familiar with back-end tool flows and scripts to automate the implementation of APR.
- Work with RTL designer to optimize the physical design implementation, and minimizes timing closure risks.
Requirements:
- BS in EE/CS with 2+ years of relevant experience, MS with 1+ years of relevant experience;
- Experience with several APR tools, timing tools, parasitic extraction methods, standard cell library timing models and scripting languages.
- Hands on Auto-P&R of complex SoC.
职位职责：
负责复杂数字设计的后端自动或手动布局和时序逼近开发验证工作。熟悉APR的工具流程及脚本。
职位要求：
- CS/EE硕士学位，1年以上相关工作经验；或CS/EE学士学位，2年以上相关工作经验
- 熟练使用APR工具，时序分析工具。
- 熟练的中英文交流能力

Job Title: Senior IC Back-end Layout Engineer 资深IC后端设计工程师 (1 position)
Job Responsibilities:
- Responsible for developing and verifying complex digital designs with an emphasis on backend tasks of automated and manual placement and timing closure.
- Develop tool flows and scripts to automate the implementation of APR.
- Work with RTL designer to optimize the physical design implementation, and minimizes timing closure risks.
Requirements:
- BS in EE/CS with 3+ years of relevant experience, MS with 2+ years of relevant experience;
- Experience with several APR tools, timing tools, parasitic extraction methods, standard cell library timing models and scripting languages.
- Hands on Auto-P&R of complex SoC.
- Prior knowledge and experience of CAD tool development are required. Prior experience with Primetime and Astro would be beneficial.
- Good team player with excellent communication skill in both Chinese and English.
职位职责：
负责复杂数字设计的后端自动或手动布局和时序逼近开发验证工作。开发能自动执行APR的工具流程及脚本。优化结构设计，减少时序逼近风险。
职位要求：
- CS/EE硕士学位，2年以上相关工作经验；或CS/EE学士学位，3年以上相关工作经验
- 熟练使用APR工具，时序工具。熟悉模型抽取方法，标准单元库时序模型和脚本语言
- 熟悉复杂片上系统的自动布局布线
- 会使用CAD，能用Primetime 和 Astro者优先
- 熟练的中英文交流能力

Job Title: Senior IC Circuit Designer 资深IC电路设计工程师 (1 position)
Job Responsibilities:
Responsible for full-custom circuit implementation, debug, schematic entry, simulations, layout supervision and bench characterization.
Requirements:
- MSEE with at least 2 years of CMOS circuit design experience.
- Familiar with usage of major EDA tools: SE, Hspice and Hsim.
- Highly motivated to complete assignment in a dynamic working environment.
- Good documentation and communication skill,in both Chinese and English
- It is essential that the individual has strong desires to learn and explore new technologies and is able to show good analysis and problem solving skills.
- Experience on PLL and High Speed IO designs is a plus.
职位职责：
负责电路执行，调试，原理图输入，仿真，布局管理和测试描述
职位要求：
- E.E硕士学历，并具有两年以上CMOS电路设计经验
- 熟练使用主要的EDA工具，如SE, Hspice 和 Hsim。
- 优秀的中英文交流及文档书写能力
- 具有较好的解决及分析问题的能力
- 有PLL和高速IO设计经验者优先

Job Title: Product Engineering Manager 产品经理 （1 position）
Job Responsibilities:
- New product introduction and release to production.
- New product characterization and spec validation.
- Yield analysis and improvement for new and sustaining products/processes.
- Test specifications and test program development.
- Test coverage improvement.
- Cost reduction implementations.
Requirements:
- BSEE or MSEE degree and 5+ years of relevant working experience.
- Experience with ATE testers, preferably Agilent 93000 or Credence Sapphire.
- Knowledge of FPGA product test is definite plus.
- Familiar with IC fab process, package, assembly and test.
- Excellent verbal and written communication skills.
- Excellent problem solving skills.

Job Title: Sales Account Manager 销售客户经理 （1 position）
Job Responsibilities:
* Aggressively grow Agates business to broad base customers and increase Agates presence
* manage direct customers as well as sales channels
* manage channel sales team and local distributors and work closely with the field applications engineering (FAE) team to win designs and build strong customer relationships
* deliver positive message and Agate value proposition to the Channel
Requirements:
* BSEE or equivalent with a minimum of 2 years sales or technical experience in the semiconductor industry including a minimum of 1 years experience in sales.
* Proven success in managing major accounts and distributors in China is required.
* Good communication skills are required.
* An ASIC or PLD related background is a plus.
职位职责：
- 积极拓展客户，提升矽正的知名度；
- 管理直销客户和销售渠道；
- 管理销售团队和各地分销商，和FAE团队一起紧密合作，维系和加强客户关系；
- 向销售渠道传达正面信息和矽正价值观。
职位要求：
- 具有电子工程专业本科学位，或者在半导体行业至少2年的销售或技术工作经验，其中至少1年的销售经验。 - 必须拥有在中国地区管理大客户和经销商的成功案例。
- 出色的沟通技能。
- 具有ASIC或PLD的相关背景者优先。




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