- 工作地点：北京
- 职位：Logic Design Engineer (Intern)
- 信息来源：中华英才网
说明：
【Group./Dept.】Logic此信息由中华英才网审核并发布（查看原发布网址），应届生求职网转载该信息只是出于传递更多就业招聘信息，促进大学生就业的目的。如您对此转载信息有疑义，请与原信息发布者中华英才网核实，并请同时联系本站处理该转载信息。
【Responsibilities】
1. Logic Design, timing verification and physical synthesis;
2. System verification and debugging;
3. Functional model development;
4. Test vector development and debugging
【Requirements】
1. Postgraduate student（the 1st year or the 2nd year）majoring in microelectronic, computer science or related;
2. Knowledge of digital circuit design, computer system architecture;
3. Familiar with Verilog/VHDL and behavior modeling;
4. Experience in design tools such as simulator, logic synthesis;
5. Full time work at least 4 days a week in half a year.
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