IC Designer

标 题: IC Designer
发信站: 水木社区 (Wed Aug 8 18:43:53 2007), 站内

Company Introduction:
Agate Logic is a global pioneer of the innovative configurable system-on-chip (SoC) technologies. The company offers a full spectrum of SoC devices, software design tools, intellectual property (IP), and design services.

Agate Logic is headquartered in U.S.A., and is currently hiring engineering and field support talents in its new Beijing R&D center.

　　
Agate Logic 致力于可配置系统芯片的开发与销售，采用本土化的芯片制造商，目标定位于多种应用类市场领域，例如通信设备、工业控制系统、消费类电子产品等。我们的产品以可配置、可编程、多功能为特点，提供了一个通用的设计平台，可以运用于任何领域。我们的通用芯片平台，高效的EDA软件加上可配置的IP模块，能为系统提供商带来更多的便利。

Agate Logic是全球领先的CSoC芯片设计公司，公司总部位于美国加州，由几位留美博士共同创立，已有超过五年的历史。现在致力于发展中国的业务，推动中国本土芯片产业的发展，分别在北京和上海设立了研发和销售中心。Agate Logic北京研发中心现位于中关村科技园区清华科技园内。

Agate Logic在北京成立的研发中心是我们的一项重要战略，吸纳优秀的软件和硬件技术人才是确保我公司保持健康成长的关键。我们迫切需要拥有各类技术的优秀工程师加盟我公司。

地址：北京海淀区清华大学清华科技园
E-mail: hr@

Job Title: IC Front-end Design Engineer IC前端设计工程师 (1 position)
Job Responsibilities:
Independently design, verify re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- B.S. with at least 2 years’ working experience, or M.S. with 1 years’ project experience in logic design.
- Good knowledge on Verilog/VHDL.
- Familiar with logic synthesis, simulation and verification tools, such as DC, Modelsim/VCS.
- Good programming skills in script language, such as TCL, perl.
- Good documentation and communication skill, in both Chinese and English
Preferences:
- Familiar with Static Timing Analysis using PrimeTime.
- Skillful in shell scripts, Python, and/or Perl.
职位职责：
独立地对ASIC 或 FPGA的优化硬件可重用HDL模型进行描述，设计，执行，并验证
职位要求：
- 大学本科以上学历，有2年工作经验；或者硕士学历，有1年逻辑设计项目经验
- 熟悉Verilog/VHDL，熟练使用逻辑综合，仿真和验证工具，如DC, Modelsim/VCS
符合以下条件者优先考虑：
- 较好的脚本语言编程能力，如TCL, perl.
- 能够熟练使用PrimeTime 做静态时序分析，精通Shell脚本，Python，Perl

Job Title: Senior IC Front-end Design Engineer 资深IC前端设计工程师 (1 position)
Job Responsibilities:
Independently specify, design, implement, verify hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- M.S. with at least 2 years of experience, or B.S. with 4 years’ experience in processor, memory controller, PCI, or networking equipment design;
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools;
- Familiar with Front-end Flow, logic synthesis using Synopsys Design Compiler, timing check with PrimeTime, test bench development and verification and design-for-test scan insertion;
- Have a track record of successful achievement in complex design projects;
- Good programming skills in script language, such as tcl, perl.
- Good documentation and communication skill, in both Chinese and English.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Skillful in C, C++, shell scripts, Python, and/or Perl.
职位职责：
独立地对ASIC 或 FPGA的优化硬件可重用HDL模型进行描述，设计，执行，并验证
职位要求：
- 硕士学历2年以上工作经验；或者本科学历，有4年以上在处理器，内存控制其，PCI，或网络相关芯片设计等方面工作经验
- Verilog，VHDL设计经验丰富，熟练使用逻辑综合，仿真和验证工具
- 熟悉前端设计流程，熟练使用Synopsys Design Compiler, PrimeTime
- 有很强的脚本语言编程能力，如TCL, perl
- 优秀的中英文交流及文档书写能力
- 熟悉FPGA者优先

Job Title: Senior Verification Engineer 资深验证工程师 (1 position)
Job Responsibilities:
Independently specify, design complex SoC verification platform to verify complex SoC.
Requirements:
- M.S. in E.E. with more than 3 years’ complex SoC verification experience;
- Hands on HDL RTL coding, and assertion-based verification methods;
- Familiar with and related EDA verification tools (such as VCS +Vera, Questasim) ;
- Familiar with C, system-verilog language;
- Good documentation and communication skill,in both Chinese and English.
Preferences:
- Familiar with script languages such as csh, tcl or perl
- Familiar with FPGA
职位职责：
独立地设计复杂的片上系统验证平台
职位要求：
- E.E．硕士学历，3年以上复杂片上系统验证经验
- 熟悉RTL级HDL编码及验证方法
- 熟练使用相关EDA验证工具，如VCS +Vera, Questasim等
- 熟悉C, System-Verilog 语言
- 优秀的中英文交流及文档书写能力

Job Title: Verification Engineer 验证工程师 (1 position)
Job Responsibilities:
To do the complex SoC function verification and gate-level netlist verification.
Requirements:
- Bachelor in E.E. with 2 to 3 years project experience or Master in E.E. with 1 to 2 years’s SoC verification experience;
- Hands on HDL RTL coding, familiar with Assertion-based verification language;
- Familiar with and related EDA verification tools.
Preferences:
- Familiar with script languages such as csh, tcl or perl
- Familiar with C, System-Verilog language
- Familiar with FPGA
职位职责：
负责复杂片上系统功能及门级网表验证
职位要求：
- E.E学士学位，2到3年相关工作经验；或E.E硕士学位，1到2年片上系统验证经验。
- 熟悉RTL级HDL编码及验证语言
- 熟悉相关EDA验证工具
- 熟悉csh, tcl 或 perl等脚本语言，C, System-Verilog 语言，FPGA者优先

Job Title: Senior IC Circuit Designer 资深IC电路设计工程师 (1 position)
Job Responsibilities:
Responsible for full-custom circuit implementation, debug, schematic entry, simulations, layout supervision and bench characterization.
Requirements:
- MSEE with at least 2 years of CMOS circuit design experience.
- Familiar with usage of major EDA tools: SE, Hspice and Hsim.
- Highly motivated to complete assignment in a dynamic working environment.
- Good documentation and communication skill,in both Chinese and English
- It is essential that the individual has strong desires to learn and explore new technologies and is able to show good analysis and problem solving skills.
- Experience on PLL and High Speed IO designs is a plus.
职位职责：
负责电路执行，调试，原理图输入，仿真，布局管理和测试描述
职位要求：
- E.E硕士学历，并具有两年以上CMOS电路设计经验
- 熟练使用主要的EDA工具，如SE, Hspice 和 Hsim。
- 优秀的中英文交流及文档书写能力
- 具有较好的解决及分析问题的能力
- 有PLL和高速IO设计经验者优先

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