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Responsibility:
- Physical design from RTL or netlist to GDSII;
- Typical tasks include Logic Rule Checker, Design for Testability, Floorplan, Clock tree generation, Place and Route, Crosstalk analysis and IR Drop check, Static Timing Analysis and test vector generation;
- Work on 0.18m, 0.13m and 90nm processes and design methodologies;
Requirements:
- Candidate must have a Bachelor or above in electronics engineering or related field;
- Good analytical and problem solving skills;
- Good communication skills, English language with CET 4;
职位描述:
- 完成RTL设计、版图设计到GDSII的流程的物理设计;
- DRC/LVS,可测性设计,Floorplan,Clock Tree 生成, 布线,串绕分析,IR Drop检查,STA分析,test vector生成等一系列的设计任务的完成;
- 对于0.18工艺, 0.13工艺 及 90纳米工艺,做后端设计;
职位要求:
- 具备微电子或工程类相关专业的学士或硕士学位;
- 较强的独立分析和解决问题的能力;
- 良好的沟通能力,英语四级以上.