四、岗位名称:ASIC/FPGA assitant engineer(Internship) 职位描述: Job Description:1. Have the telecom background to understand the system requir ement; 2.Have experience on VHDL/Verilog RTL coding, simulation, synthesis 3. Develop module/chip level verification strategies. Build and maintain simul ation/regression environment, Create test plans from module level to chip leve l ; Write test benches for functional verification using HDL or ANSI C. 4.Debug/test the chip design in board/system level cooperate with HW engineers . 6.Good communication and writing skill, good team work spirit. 职位要求: 1、电子工程专业或类似 2、06年入学的研究生 3、有硬件项目开发的实习或者工作经验 4、勤学苦干、刻苦耐劳精神,主动积极的学习愿望,做事有责任心。 5、每周保证4个工作日,持续半年,一年以上更佳。