Company profile
Founded in 2001, VeriSilicon Holdings Co., Ltd. ("VeriSilicon") is a fast growing silicon solutions company providing products and services that enable customers to meet their chip design objectives, accelerate development programs and deliver market proven silicon products - on time and at lower cost.
VeriSilicon specializes in providing expert design services, market leading ZSP® licensable cores and platforms, industry standard semiconductor IP and scalable ASIC turnkey services across a broad range of application markets, including multimedia, voice and wireless communications. VeriSilicon has an extensive track record of accelerating customer ASIC designs from initial specification to silicon, achieving first silicon success - on time and on spec - and taking customer silicon through to volume production, utilizing its partner network of leading wafer foundries and packaging and test companies in Asia Pacific and China. VeriSilicons global customer base of market leading multi-nationals to fabless start-up companies benefit from shorter development cycles, reduced cost of ownership and economies of scale provided by VeriSilicons value-added IP platforms, flexible engagement model, superior supply chain management and strong service culture.
With more than 180 highly skilled engineers and design centers worldwide, VeriSilicons customers are able to leverage a truly global design services company to support their silicon projects and meet design and cost objectives. VeriSilicon has design, operation and sales and support offices in Santa Clara, California, Dallas, Texas, Shanghai and Beijing, China, Taipei, Taiwan, Tokyo, Japan, Nice, France and Seoul, Korea.
In 2005, VeriSilicon was ranked No.3 in Deloitte Technology Fast 50 China and No.6 in Deloitte Technology Fast 500 Asia Pacific. VeriSilicon was named one of the Red Herrings 100 Private Companies of Asia and was also selected as one of EE Times 60 Emerging Startups.
公司介绍
芯原股份有限公司成立于2001年，是一家发展迅速的芯片产品解决方案公司，公司提供的产品和服务使客户能够达到他们芯片设计的目标，加速开发项目并以较低的成本及时提供市场公认的芯片产品。
芯原专注于在多媒体、语音和无线通信等广大的应用市场提供专家设计服务、市场领先的ZSP®授权内核和平台、业内标准的半导体 IP 以及可升级的 ASIC 全包服务。芯原在以下方面拥有广泛的经验：通过利用其在亚太（包括中国）领先的晶圆代工厂和包装测试公司的合作伙伴网络加速客户 ASIC 设计（从初步的规格到芯片产品）、在芯片产品方面按时按规格取一次成功（First Silicon Success）以及使客户芯片产品实现量产。芯原的客户大多是基于全球市场主导地位的跨国公司，通过芯原为他们提供的增值的IP平台、灵活的沟通模式、有效的供应链管理以及强大的支持服务，使其能够真正有效的缩短研发周期、降低开发成本、并最终实现规模型经济。
芯原在全球拥有180多个高级工程师和设计中心，客户能够真正利用全球设计服务公司为他们的芯片项目提供支持并实现设计和成本目标。芯原在美国加州圣塔克拉拉、德州达拉斯、中国北京、中国台湾台北、日本东京、法国尼斯和韩国首尔拥有设计、经营和销售支持办事处。
2005年，芯原排名德勤中国高科技、高成长50强 (Deloitte Technology Fast 50 China) 第三名以及德勤亚太区高科技高成长500强 (Deloitte Technology Fast 500 Asia Pacific) 第六名。芯原还荣获 Red Herring 亚洲尚未上市企业100强企业 (Red Herrings 100 Private Companies of Asia) 之一，并入选 EE Times 全球60家最具潜力半导体初创公司 (EE Times 60 Emerging Startups)。
Wayne Wei-Ming Dai
Wayne Dai is the founder, Chairman, President and CEO of VeriSilicon Holdings Co., Ltd. He was the Co-Chairman and Chief Technology Officer of Celestry Technologies, Inc., which was acquired by Cadence Design Systems in 2002. Prior to that, he was the founder, Chairman, and CEO of Ultima Interconnect Technology, Inc., one of the predecessor companies to Celestry.
He was the founding Chairman of the IEEE Multi-Chip Module Conference and the founding Chairman of IEEE Symposium on IC/Package Design Integration. He was an Associate Editor for IEEE Transactions on Circuits and Systems, and an Associate Editor for IEEE Transactions on VLSI Systems. He has published over 100 papers in technical journals and conferences and received the Presidential Young Investigator Award from the President of United States in 1990. In the year of 2005, Dr. Dai was elected as one the top ten venture-backed entrepreneurs in China, and elected as one of the 2005 top ten talents of science and technology in China.
Wayne Dai received his B.A. degree in Computer Science and his Ph.D. degree in Electrical Engineering, both from the University of California at Berkeley. He was a Professor in the department of Computer Engineering at the University of California at Santa Cruz.
戴伟民，Wayne Dai
戴博士是芯原股份有限公司公司的创始人, 董事长兼总裁。他曾出任美国Celestry公司（现已被Cadence并购）董事长兼首席技术长，还曾是美国Celestry公司前身之一，美国Ultima的创始人、 董事长兼总裁。
戴博士是世界电子工程师协会多芯片模块国际会议和世界电子工程师协会芯片封装综合设计研讨会的创办主席。他曾担任世界电子工程师协会电路和系统论文月刊和超大规模集成电路系统论文月刊的副编辑，在各类技术刊物和会议上发表过100多篇论文。戴博士于1990年荣获美国总统青年研究奖，2005年他在中国获得“10大创业企业家”称号，并当选为“2005年中国十大科技英才”。
戴博士在美国加州大学伯克利分校获得了计算机科学学士学位和电机工程博士学位，曾任加州大学圣克鲁兹分校计算机工程学教授。
System Application Engineer
系统应用工程师
Job Descriptions:
l Design and develop various applications for IC products, including arrangement and debug of hardware on board level, and development of firmware (like BSP, Driver, API, etc.)
IC产品的应用设计开发，包括板级的硬件设计，调试，相关固件firmware（如RTOS的BSP，driver, API等等）的开发
l Conduct FPGA verification of SOC, IC and IP circuits
SOC,IC和IP的FPGA验证工作
l Carry out in-house tests for IC products and SOC systems developed by the company
IC和SOC的实验室测试工作
l Provide technical support for customers regarding product applications
为客户提供本公司产品的应用技术支持
Requirements:
l Master’s degree, majored in CS, EE or Automation
计算机、电子工程或自动控制专业硕士
l Good programming skills in C and assembly languages
有良好的C语言和汇编语言的编程能力
l Understand ARM architecture and its peripheral systems, understanding of ZSP(a type of DSP) is a plus
熟悉ARM体系及其外部系统, 熟悉ZSP(一种DSP)尤佳
l Good knowledge about FPGA application, Verilog or VHDL hardware language. Internship or project experience in FPGA synthesis and reuse is preferred
熟悉FPGA的应用，了解VHDL或Verilog 硬件描述语言。有FPGA综合和设计复用方面的实习或项目经验者优先
l Good knowledge about Embedded Operating System, for example, development of embedded LINUX and its driver.
熟悉嵌入式操作系统，如嵌入式Linux及其驱动程序的开发
l Self motivated, good communication and team work skills are a must
富有事业心和团队合作精神，沟通表达能力良好
SOC Design Engineer
芯片系统设计工程师
Responsibilities:
l Capable of independently contributing to and working on designs of ASIC components/modules in terms of RTL coding, logic synthesis, STA and DFT considerations
胜任RTL代码，逻辑综合，STA和DFT方面ASIC元器件和模块的设计工作，能够独立完成任务
l Work closely with verification team, physical design, test and FPGA engineers to solve functional verification, floor-plan, timing and test issues
密切配合验证工程师、版图工程师、测试工程师以及FPGA工程师，解决功能性验证、平面版图、时序及测试等方面的问题。
l Be responsible for micro-architecture and implementations of ASIC functions all the way to chip-level formal verification, timing analysis and bridge to physical design
负责从微结构、ASIC功能实现、芯片级正式验证乃至时序分析之整个过程，搭建通向物理设计的桥梁。
Requirements:
l MS/PhD, with at least 1+ years of experience in ASIC design, including course projects
硕士/博士学历，至少一年ASIC设计经验，包括课程项目
l Possessing the independent mastery of EDA tools and capability of solving technical issues in one of the following areas is a must：
Synopsys and/or Cadence tools; design specification bring-up, RTL coding and style critique, chip-level synthesis, static timing analysis, formal verification and scan-chain insertion
熟练应用EDA工具，能够独立解决至少一项下述领域中的技术问题：
Synopsys 或Cadence 工具；设计规格的制定；RTL代码和格式的审查；芯片级集成；静态时序分析；验证和扫描链嵌入
l Solid knowledge and proven track record in design flow and methodologies for deep submicron ASIC development is a plus
在深亚ASIC开发设计流程和方法上有着丰富知识及成功经验者优先
l Strong understanding of ASIC design issues and considerations relating to silicon success
熟谙ASIC设计中的问题及硅验证事项
l Self motivated, good communication and team work skills are a must
富有事业心和团队合作精神，沟通表达能力良好
Physical Layo, ut/QA Engineer
物理版图设计/质量保证工程师
Job Descriptions:
l Design the layout of deep sub-micron CMOS circuits;
设计CMOS 深亚微米电路版图
l Develop the layout of standard logic cells, memory and IO cells;
开发标准逻辑单元、存储器及输入输出单元版图
l Devise the layout of analog block, memory and High-speed IO cells;
设计模拟电路、存储器和高速IO单元版图
l Conduct layout physical verification.
实施版图物理验证
Requirements:
l BE majored in EE, CS, Physics, Automation or relevant discipline;
电子工程、计算机、物理、自动化或相关专业本科学历
l Course knowledge in at least one of the following areas is required: Analog block, Memory and High-speed IO layout; training experience/certificate on layout is preferred;
具备模拟电路, 存储器或高速IO版图方面一门以上课程知识，有版图培训经历或证书者优先
l Familiar with design rules in deep submicron processing;
熟悉深亚微米工艺设计规则
l Skills in DRC/LVS debugging;
有DRC/LVS 查错技能
l Self motivated, good communication and team work skills are a must.
富有事业心和团队合作精神，沟通表达能力良好
Design Implementation Engineer
设计实现工程师
Job responsibilities:
l Logic synthesis and timing analysis
逻辑综合以及时序分析
l DFT (design-for-test) and ATPG
测试电路设计及自动测试向量生成
l Deep sub-micron chip floor plan
CMOS 深亚微米芯片平面布局
l CTS, Power plan, Placement & Routing, and SDF
CTS, 电源方案, 布局布线以及SDF
l Whole chip DRC/LVS
芯片级 DRC/LVS
Requirements:
l Master’s degree or above, majored in EE, CS, Physics or relevant discipline
电子工程，计算机科学或物理学等相关专业硕士或更高学历
l Course knowledge about logic synthesis, DFT, STA, noise and crosstalk analysis, physical design, EDA tool and tape-out issue is a must, project experience in one of the above fields is required
具备逻辑综合，测试电路设计，静态时序分析，噪声及串扰分析，物理版图设计、EDA 工具以及流片课程知识，有部分相关项目经验
l Self motivated, good communication and team work skills, steady and surefooted work attitude are highly wanted
富有事业心和团队合作精神，沟通表达能力良好, 工作踏实稳定
Analog Circuit Design Engineer
模拟电路设计工程师
Responsibilities:
l Devise and develop deep sub-micron CMOS analog circuit
设计开发CMOS 深亚微米模拟电路
l Guide and/or supervise layout
指导、监督版图设计
l Assist in the design of test boards so as to debug and verify test chips
协助设计测试板, 调试验证测试芯片
Requirements:
l MS/PHD degree, majored in EE
电子工程专业硕士/博士学历
l Course knowledge and project experience in the related areas
相关课程知识及项目经验
l Good understanding about one of the following disciplines: low voltage／low noise OPA, ADC & DAC, PLL/DLL, high speed IO, RF and other analog blocks
熟悉以下单项或多项设计概念：低电压、低噪音OPA；ADC&DAC；PLL/DLL；高速IO；RF和其它模拟电路
l Self motivated, good communication and team work skills are a must
富有事业心和团队合作精神，沟通表达能力良好
招聘时间：2007-11-20 13:30－－１７：００
招聘地点：榴园新华厅
