华为海思招聘ASIC Design Engineer/Digital Verification Engineer

标 题: 华为海思招聘ASIC Design Engineer/Digital Verification Engineer
发信站: 水木社区 (Wed Jan 23 10:38:04 2008), 站内

欢迎优秀应届毕业生和有工作经验人士投递
职位：
1.ASIC Design Engineer.
Being ASIC Design Engineer, will focus on the whole front-end design flow of Ethernet related products(from RTL to tapeout), both block level and chip level. Co-operate with the verification engineer for the block level and chip level verification
The candidate should possess excellent interpersonal, communication and team skills, and have a good command of oral and written English.
- 2+ years of experience on asic chip front-end design required, at least one chip tapeout experience
- familiar with common EDA design tools like VCS, DC and PT required, backend flow understanding preferred
- 0.13um or more advanced technology design flow experience preferred
- Network related background especially LAN and Ethernet knowledge related asic chip design experience preferred
- BSEE/CS or higher is required


2,Digital Verification Engineer
Job Description:
The work responsibility will be the development of the testbench of both block level and chip level, write the verification model of important functions, co-operate with design engineer for block level and chip level verification.
Position Requirement:
-excellent interpersonal, communication and team skills, and have a good command of oral and written English.
-2+ years of experience on asic chip verification flow with assertion language, at least one chip tapeout experience, front-end understanding preferred
-familiar with common EDA simulation tools like VCS required, VERA/SystemVerilog experience Preferred
-0.13um or more advanced technology chip experience preferred
-Network related background especially LAN and Ethernet project experience preferred
-ARM SOC development experience preferred
-BSEE/CS or higher is required


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