- 工作地点：上海
- 职位：2009招聘
- 信息来源：西安电子科技大学就业网
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芯原微电子（上海）有限公司2008年大学专场招聘会
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发布者：[本站编辑] 来源：[西安电子科技大学毕业生就业信息网] 浏览：[160]
公司介绍
芯原股份有限公司成立于2001年，是一家发展迅速的芯片产品解决方案公司，公司提供的产品和服务使客户能够达到他们芯片设计的目标，加速开发项目并以较低的成本及时提供市场公认的芯片产品。
芯原专注于在多媒体、语音和无线通信等广大的应用市场提供专家设计服务、市场领先的ZSP®授权内核和平台、业内标准的半导体 IP 以及可升级的 ASIC 全包服务。芯原在以下方面拥有广泛的经验：通过利用其在亚太（包括中国）领先的晶圆代工厂和包装测试公司的合作伙伴网络加速客户 ASIC 设计（从初步的规格到芯片产品）、在芯片产品方面按时按规格取一次成功（First Silicon Success）以及使客户芯片产品实现量产。芯原的客户大多是基于全球市场主导地位的跨国公司，通过芯原为他们提供的增值的IP平台、灵活的沟通模式、有效的供应链管理以及强大的支持服务，使其能够真正有效的缩短研发周期、降低开发成本、并最终实现规模型经济。
芯原在全球拥有180多个高级工程师和设计中心，客户能够真正利用全球设计服务公司为他们的芯片项目提供支持并实现设计和成本目标。芯原在美国加州圣塔克拉拉、德州达拉斯、中国北京、中国台湾台北、日本东京、法国尼斯和韩国首尔拥有设计、经营和销售支持办事处。
Founded in 2001, VeriSilicon Holdings Co., Ltd. ("VeriSilicon") is a fast growing silicon solutions company providing products and services that enable customers to meet their chip design objectives, accelerate development programs and deliver market proven silicon products - on time and at lower cost.
VeriSilicon specializes in providing expert design services, market leading ZSP® licensable cores and platforms, industry standard semiconductor IP and scalable ASIC turnkey services across a broad range of application markets, including multimedia, voice and wireless communications. VeriSilicon has an extensive track record of accelerating customer ASIC designs from initial specification to silicon, achieving first silicon success - on time and on spec - and taking customer silicon through to volume production, utilizing its partner network of leading wafer foundries and packaging and test companies in Asia Pacific and China. VeriSilicons global customer base of market leading multi-nationals to fabless start-up companies benefit from shorter development cycles, reduced cost of ownership and economies of scale provided by VeriSilicons value-added IP platforms, flexible engagement model, superior supply chain management and strong service culture.
With more than 180 highly skilled engineers and design centers worldwide, VeriSilicons customers are able to leverage a truly global design services company to support their silicon projects and meet design and cost objectives. VeriSilicon has design, operation and sales and support offices in
职位和要求
模拟电路设计工程师
Analog Circuit Design Engineer
工作描述：
l 设计开发CMOS 深亚微米模拟电路
l 指导、监督版图设计
l 协助设计测试板, 调试验证测试芯片
职位要求：
l 电子工程专业硕士/博士学历
l 相关课程知识及项目经验
l 熟悉以下单项或多项设计经验：低电压、低噪音OPA；ADC&DAC；PLL&DLL；高速IO；RF和其他模拟电路
l 富有事业心和团队合作精神，沟通表达能力良好
l 以上职位同时欢迎应届生投递简历应聘
Responsibilities:
l Devise and develop deep sub-micron CMOS analog circuit
l Guide and/or supervise layou
l Assist in the design of test boards so as to debug and verify test chips
Requirements:
l MS/PHD degree, majored in EE
l Course knowledge and project experience in the related areas
l Good understanding about one of the following disciplines: low voltage／low noise OPA, ADC&DAC, PLL/DLL, high speed IO, RF and other analog blocks
l Self motivated, good communication and team work skills are a must
芯片系统设计工程师
SoC Design Engineer
工作描述：
l 胜任RTL代码，逻辑综合，STA和DFT方面ASIC元器件和模块的设计工作，能够独立完成任务
l 密切配合验证工程师、版图工程师、测试工程师以及FPGA工程师，解决功能性验证、平面版图、时序及测试等方面的问题
l 负责从微结构、ASIC功能实现、芯片级正式验证乃至时序分析之整个过程，搭建通向物理设计的桥梁
职位要求：
l ME or above, majored in EE, CS or relevant discipline;
l 硕士/博士学历，至少一年ASIC设计经验，包括课程项目
l 一年以上行为级编程、综合、时序验证、扫描链插入工作经验
l 熟练应用EDA工具，能够独立解决至少一项下述领域中的技术问题：Synopsys或Cadence工具；设计规格的制定，RTL代码和格式的审查；芯片级集成；静态时序分析；验证和扫描链嵌入
l 深亚ASIC开发设计流程和方法上有着丰富知识及成功经验者优先
l 熟谙ASIC设计中的问题及硅验证事项
l 富有事业心和团队合作精神，沟通表达能力良好
l 以上职位同时欢迎应届生投递简历应聘
Responsibilities:
l Capable of independently contributing to and working on designs of ASIC components/modules in terms of RTL coding, logic synthesis, STA and DFE considerations
l Work closely with verification team, physical design, test and FPGA engineers to slove functional verification, floor-plan, timing and test issues
l Be responsible for micro-architecture and implementations of ASIC functions all the way to chip-level formal verification, timing analysis and bridge to physical design
Requirements:
l ME/PHD, with at least 1+ years of experience in ASIC design, including course projects
l Possessing the independent mastery of EDA tools and capability of solving technical issues in one of the following areas is a must
Synopsys and/or Cadence tools; design specification bring-up, RTL clding and style critique, chip-level synthesis, static timing analysis, formal verification and scan-chain insertion
l Solid knowledge and proven track record in design flow and methodologies for deep submicron ASIC development is a plus
l Strong understanding of ASIC design issues and considerations relating to silicon success
l Self motivated, good communication and team work skills are a must
设计实现工程师
Design Implementation Engineer
工作描述：
l 逻辑综合以及时序分析
l 测试电路设计及自动测试向量生成
l CMOS深亚微米芯片平面布局
l CTS，电源方案，布局布线以及SDF
l 芯片级DRC/LVS
职位要求：
l 电子工程，计算机科学或物理学等相关专业硕士或更高学历
l 具备逻辑综合，测试电路设计，静态时序分析，噪声及串扰分析，物理版图设计、EDA工具以及流片课程知识，有部分相关项目经验
l 富有事业心和团队合作精神，沟通表达能力良好，工作踏实稳定
l 以上职位同时欢迎应届生投递简历应聘
Responsibilities:
l Logic Synthesis and timing analysis
l DFT(design-for-test) and ATPG
l CTS, Power plan, Placement & Routing, and SDF
l Whole chip DRC/LVS
Requirements:
l Master’s degree or above, majored in EE, CS, Physics or relevant discipline
l Course knowledge about logic synthesis, DFT, STA, noise and crosstalk analysis, physical design, EDA tool and tape-out issue is a must, project experience in one of the above fields is required
l Self motivated, good communication and team work skills, steady and surefooted work attitude are highly wanted
物理版图设计/质量保证工程师
Physical Layout/QA Engineer
工作描述：
l 设计CMOS 深亚微米电路版图
l 开发标准逻辑单元、存储器及输入输出单元版图
l 设计模拟电路, 存储器和高速IO单元版图
l 实施版图物理验证
职位要求：
l 电子工程,计算机,物理, 自动化或相关专业本科学历
l 具备模拟电路，存储器或高速IO版图方面一门以上课程知识，有版图培训经历或证书者优先
l 熟悉深亚微米工艺设计规则
l 有DRC/LVS 查错技能
l 富有事业心和团队合作精神，沟通表达能力良好
l 以上职位同时欢迎应届生投递简历应聘
Responsibilities:
l Design the layout of deep sub-micron CMOS circuits
l Develop the layout of standard logic cells, memory and IO cells
l Devise the layout of analog block, memory and High-speed IO cells
l Conduct layout physical verification
Requirements:
l BE majored in EE, CS, Physics, Automation or relevant discipline
l Course knowledge in at least one of the following areas is required: Analog block, Memory and High-speed IO layout; training experience/certificate on layout is preferred
l Familiar with design rules in deep submicron processing
l Skills in DRC/LVS debugging
l Self motivated, good communication and team work skills are a must
嵌入式软件开发工程师/高级工程师（DSP）
Embedded Software Development Engineer/Sr. Engineer(DSP)
工作描述
l 开发以及移植DSP音频解码器
l 优化音频解码器，使之高度适配于指定的DSP系统
l 设计友好的解码引擎对外接口
职位要求
l 电子工程或计算机工程专业硕士/博士学历
l 一定的信号/视频处理经验
l 扎实的C/C++基础
l 熟悉计算机架构，具备DSP汇编语言编程经验
l 拥有关于下述一项或多项编码/解码器的实际工作经验：mp3, AMR, AAC, WMA, RealAudio
l 了解视频编码/解码器
l 了解嵌入式软件系统
l 良好的英语听说能力
l 工作具有主动性，良好的团队合作精神
l 以上职位同时欢迎应届生投递简历应聘
Responsibilities:
l Implement and port audio decoder on DSP platform.
l Optimize audio decoder to make it highly suitable for the specified DSP system.
l Provide well-defined API to encapsulate the decode engine.
Requirements:
l MS or PhD degrees in Electronic Engineering, Computer Engineering;
l Solid background in Signal/video processing
l Good programming skills in C/C++
l Good understanding of computer architecture. Experiences of assembly language of DSP.
l Hand-on experience with one or more of these codecs: mp3, AMR, AAC, WMA, RealAudio
l Basic understanding of video codec
l Good understanding of embedded software;
l Good written English;
l Self-motivated; good team-work spirit.
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