招聘英才：
（1）Logic Design Engineer or trainee
ASIC逻辑设计工程师或实习生（数名）
Responsibility.职责描述：
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.使用RTL代码设计数字逻辑电路（用于混合信号IC）
B)Write RTL code for custom designed blocks such as SRAM and adder blocks.编写客户定制RTL代码，例：SRAM，加法器等
C)Define micro architecture of digital part of the mixed signal IC.定义混合信号IC数字部分微架构
D)Verification of the logic blocks using test bench and Vera.使用test bech和VERA语言验证逻辑功能块
E)Use FPGA to validate the designed blocks. 使用FPGA验证设计模块
F)Write synthesis script to generate gate level netlist.编写综合教本产生门级网表
G)Analyze timing for synthesized blocks.分析综合模块时序
Requirements.任职要求：
A)1 years RTL coding experience.1年RTL代码经验
B)Understanding of concept of state-machine.了解状态机概念
C)Understanding of the concept of timing. Able to perform static timing analysis.具备时序概念，能进行静态时序分析
D)Familiar with VCS or NC-Verilog熟悉VCS 或 Verilog
E)Able to write and use test-bench to test RTL blocks.可以编写和使用测试平台测试RTL模块
F)Able to program FPGA to test logic blocks.可以使用FPGA编程测试逻辑模块
（2）Analog Circuit Design Engineer or trainee
IC模拟电路设计工程师或实习生（数名）
Responsibility.职责描述：
A)Design consumer electronics mixed signal IC设计混合信号消费电子IC
B)Responsible for product definition and micro architecture.负责产品和微结构定义
Requirements.任职要求：
A)B.S Degree in EE or Computer Science. M.S. preferred.学士学位，电子或计算机专业，硕士优先
B)Recent experience of designing TFT or STN LCD driver chip is preferred.有设计TFT或STN LCD DRIVER经验优先
C)Aware of most of the issues involved including circuit design, module, glass panel, foundry interface, packaging, ESD design, testing.了解电路设计，LCD模块，LCD PANEL ,foundry , 封装，ESD 设计，测试等领域常见问题
D)Familiar with mixed signal design and verification flow.熟悉混合信号电路设计和验证流程
E)Strong analog design background.具有模拟电路设计背景
F)1years experience in IC design.1年IC设计经验
G)Layout experienc(LVS/DRC) 需有LAYOUT 经验（LVS/DRC）
H)Detailed knowledge of reference voltage circuit, dc-dc charge pump circuit, and oscillator circuit design.具备丰富reference voltage circuit, dc-dc charge pump circuit ,oscillator circuit设计知识
I)Familiar with SPICE and mixed-signal simulation tools熟悉SPICE和混合信号仿真工具
（3）IC layout Design Engineer or trainee
IC版图设计工程师或实习生（数名）
Responsibility.职责描述：
A)Be able to verify circuits for logic circuit or analog circuit using Cadence and Synopsys tool. 负责IC版图的设计和验证
B) co-work with IC designer and layout Engineer to identify system problem.与IC设计工程师合作确定系统问题
Requirements.任职要求：
A)Bachelor or above degree in semiconductor physics or microelectronic engineering.微电子或电子专业，本科以上学历
B) At least 1 years relevant experience in circuit design. 具有版图设计工作经验1年以上，做过模拟/数字集成电路版图者优先
C) Experience in analog circuit design is preferred. 熟悉基本的CMOS半导体工艺及版图的层次
D) Familiar with CMOS craft and verification tools (eg: Dracula, caliber). 熟练应用版图验证工具，包括Dracula，Caliber等
E) Good at English. 英文熟练
（4）FAE/测试工程师（3人）（能力优秀者，可应聘：项目经理）
此职位要求有经验者！
职责描述：
A)公司产品测试
B)给客户提供技术支持，处理客户提出之异常
C)新产品的推广应用
D)手机方案设计
任职要求：
A)大学本科以上学历，电子类或相关专业
B)熟练运用PROTEL/POWERPCB/AUTOCAD 画图软件，精通数字/模拟电路
C)对Mobilephone,LCD Module 终端产品有深刻的了解，能够独立解决客户所反馈的问题。
D)有TFT LCM应用经验，能设计FPC线路，对模组显示效果尤其要敏感，熟练运用C/ASM编程
E)有二年以上Color STN &TFT LCD/LCM独立开发经验，对Color STN ,TFT LCD Driver IC有很深的了解。
F)具较强沟通能力，良好的分析和问题处理能力
欢迎您的加盟！
公司地址：深圳市南山区科技园南区中科大厦三期7楼
Email：teralane_hr@
联系电话：0755-86309521
联系人：Mr King |
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