| 公司资料 |
| 公司名称： |
柰米閃芯集成電路(上海)有限公司 |
联系部门： |
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| 联 系 人： |
Merry Li |
联系电话： |
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单位传真： |
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| 电子邮箱： |
hr@ |
单位主页： |
ww***com[点击查看] |
| 联系地址： |
上海市张江高科技园区郭守敬路４９８号６幢 |
邮政编码： |
200000 |
| 公司简介： |
柰米閃芯集成電路(上海)有限公司
Aplus Flash Technology, Inc. is a fabless IC company headquartered in Silicon Valley, USA, with branch offices in Shanghai and Taiwn. Aplus offers non-volatile memory IP and memory products. Its line of NVM IP includes ROM, OTP, NTP, EEPROM, FLASH EEPROM and FLASH, and can be embedded into a variety of communications, computing, and consumer applications. Aplus offers both standard IP blocks as well as customized ASIC designs. In addition, Aplus also develops standard memory products. Its IP blocks can be found in applications from smart cards to speech toys to microcontrollers and other IC drivers. Aplus' embedded licensees include leading global semiconductor companies and its foundry connections span worldwide in countries including Taiwan, Korea and China. Aplus also has over 60 patents (granted and pending) in the area of NVM design. For more information, please visit: ww***om.[点击查看]
ADDRESS: 498 Guoshoujing Rd.Rm.20301 Pudong New Area, Shanghai (201203)
HR Manager: Merry Li
E-MAIL: hr@
WEBSITE: ww***com[点击查看]
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| 职位资料 |
| 发布日期： |
2010年12月30日 |
人气指数： |
已被浏览5次 |
职位类别： |
全职 |
| 职位名称： |
Design Engineer、ASIC Layout Engineer、Sr. IC Layout Engineer |
| 要求专业： |
见要求 |
| 职位要求： |
Design Engineer
We are looking for logic designer to work on flash and EEPROM memory. He or she will work with senior design engineer and collaborate with a USA-based team on projects. There is tremendous opportunity for an individual with high motivation, interest, and commitment in non-volatile memory technology to become a major contributor and leader in the company. The candidate should have direct experience with schematic capture, spice simulation, logic design and verification.
Responsibilities:
Perform logic/digital/mixed-mode design.
Handle analog digital interface and participate in top level mixed-mode simulation.
Collaborate with layout team for LVS verification.
Debug and analyze product on IC chip.
Requirements
Familiar with SPICE tools (HSpice, Smart-Spice, etc.)
Familiar with logic / analog simulation tools (SILOS, Verilog, etc.)
BSEE, MSEE (preferred)
Minimum of 2 years in logic/digital design. Experience with analog design such as charge pump and voltage regulator will be a bonus.
Good communication skill in English both in writing and verbal.
Highly motivate and good work ethic.
ASIC Layout Engineer
Responsibilities:
Involve in creating non-volatile products with the latest submicron technology.
Responsible for block floor planning, cell libraries creation and layout verification.
Requirements:
BS in electronics, micro-electronics or related field.
Good command of English and team work spirit.
Have responsible and reliable personality. Details oriented.
Sr. IC Layout Engineer
Responsibility:
Creating and maintaining NVM products and IP libraries.
Leading junior layout engineers working on latest NVM technology.
Requirements:
More than 3 years experience in IC layout work.
Familiar with ESD, DFM, DRC, LVS and RC extraction.
Familiar with EPROM, EERPOM, ROM and Flash memory products.
Experience in submicron layout projects is a plus.
BS degree in micro-electronics or related field.
Good communication skill and team work spirit.
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