职位描述：
芯原微电子（上海）有限公司将于2011年10月23日（周日），下午6点30分—8点30分，在浙江大学，玉泉邵逸夫科学馆演讲厅举办2011年校园宣讲会，届时将当场进行笔试和收取简历。
工作描述：
l 能够独立完成ASIC功能模块的设计/验证任务, 具体工作包括需求分析, Spec设计, 架构定义, RTL代码，模块设计及验证, 系统集成及验证
l 密切配合系统工程师, 后端工程师、和测试工程师，解决功能性验证、后端物理实现及工程测试等方面的问题
l 负责从微结构设计、ASIC功能实现、模块/芯片级验证等工作, 搭建通向ASIC物理实现的桥梁
职位要求：
l 硕士/博士学历，电子工程或计算机科学相关专业
l 一年以上ASIC设计/验证等工作经验, 包括课程项目
l 熟练应用EDA工具(Synopsys或Cadence), 能够独立解决下述领域中的若干技术问题：
设计规格的制定，RTL代码和格式的审查, 模块设计, 系统集成；
运用SystemC进行建模；掌握SystemVerilog以及VMM/OVM验证方法学
l 深亚微米ASIC开发设计流程和方法上有着丰富知识及成功经验者优先
l 熟谙ASIC设计中的问题及硅验证事项
l 富有事业心和团队合作精神，沟通表达能力良好
Responsibilities:
l Capable of independently contributing to and working on the design/verification of ASIC function blocks in terms of Design Spec, Architecture definition, RTL coding, block design/verification, system integration/verification
l Work closely with system engineers, physical implementation designers, and testing engineers to solve functional verification, floorplan design, timing optimization/closure and testing consideration
l Be responsible for micro-architecture design, RTL design, block-/chip-level verification, as a bridge to ASIC physical implementation
Requirements:
l Master/PhD degree in EE/CS related specialties
l At least 1 years of working experience in ASIC design/verification, including course projects
l Possessing the independent mastery of EDA tools (Synopsys or Cadence) and capability of solving technical issues as below are a must
Design specification, RTL coding and style critique, block design, chip-level integration,
System-C modeling, SystemVerilog based on VMM/OVM methodology
l Solid knowledge and proven track record in design flow and methodologies for deep submicron ASIC development is a plus
l Strong understanding of ASIC design issues and deep considerations relating to silicon success
l Self motivated, team work, and good communication are a must
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