[西安]西安华芯半导体有限公司2013招聘

应届生招聘岗位

职位：

1)             数字后端设计工程师ASIC Backend Design Engineer (BE)               

2)             设计验证工程师Design and Functional Verification Engineer (DFV) 

3)             可测性设计工程师Design for Test Engineer (DFT)              

4)             数字电路设计工程师Digital Design Engineer

5)             数字前端电路设计工程师 Updated Digital Front End Design Engineer

6)             混合/模拟电路设计工程师Mixed-signal/Analog Design Engineer  

7)             混合电路设计工程师(存储器 IP)  Mixed-signal Design Engineer(Memory IP)

8)             版图设计工程师Layout Design Engineer

9)             集成电路测试工程师（设计分析与验证）IC Product Test Engineer (Design Analysis and Verification)  

10)         电路设计工程师 Circuit Design Engineer

11)         SRAM IP 设计工程师 SRAM IP Design Engineer

12)         战略合作主管Strategic Collaboration Executive

岗位职责及要求：

1）数字后端设计工程师ASIC Backend Design Engineer (BE)

Responsibilities:

1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.

2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.

3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).

4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.

5. Static Timing analysis (Prime Time) and setup/hold fix.

6. Formal Verification for equivalence checking (Formality).

7. Generation of fill structures according to technology requirements.

Requirements:

1.        Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2.        Knowledge of Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

3.        Knowledge of one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

4.        Knowledge of FE design (RTL code, flow) and verification is a plus.

5.        Good analytical and debugging skills.

6.        Good command of English.

2）设计验证工程师Design and Functional Verification Engineer (DFV)

Responsibilities:

1.       According to the design specification, be responsible for the verification plan and verification objective definition.

2.       Test-bench development(modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.

3.       Work with Random Verification methodology(VMM, OVM, UVM, eRM)

4.       Work as an independent verification engineers to check the design functionality at SOC module level and chip level.

5.       Work as interface with Front-End  and Back-End engineer to optimize or review the design architecture and implementation.

6.       Verilog or VHDL coding according to design specification or external/internal IP integration.

7.       Support the post simulation with gate-level verilog or VHDL netlist.

Requirements:

1.      Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2.      Knowledge of Verification language (SPECMAN/E-language, System-Verilog, Vera) is a plus.

3.      Knowledge of RTL coding and simulators (Modelsim, NC-sim) is a plus.

4.      Basic knowledge of script language (Perl, TCL, C-language and so on)

5.      Knowledge of 2G/3G/LTE handset base band Architecture, ARM, AHB Architecture is a plus.

6.      Knowledge about Base band chip peripheral(USB2.0/USB3.0, SSIC, MIPI) is a plus.

7.      Team oriented, love to work in young, international and highly motivated teams.

8.      Good command of English

3）可测性设计工程师Design for Test Engineer (DFT)

Responsibilities:

1. Participate in SoC level DFT architecture definition.

2. Implement DFT strategy for the SoC chips, cooperating with design team

3. Implement basic DFT schemes, including scan, boundary scan, MemBIST and LogicBIST.

4. Develop the high coverage and cost effective test patterns.

5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.

6. Support other teams for DFT related problems.

Requirements:

1. Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA

3. Good understanding of the General DFT methodology such as BIST, SCAN,JTAG and ATPG.

4. Familiar with basic Mentor/ Synopsys DFT flow and tools

5. Proficient in Verilog/VHDL language

6. Be familiar with Shell/TCL/Perl program, or skilled in C program

7. Good English communication skills

8. Self-motivated and good team player

4）数字电路设计工程师 Digital Design Engineer

Responsibilities:

1. Responsible for developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis.

2. Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.

3. Check the relative block layout implementation.

4. Test-bench and Test-pattern generation to full-cover the relative design.

Requirements:

1. Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2. Knowledge of digital design (verilog /schematic) and simulation (modelsim,NC-sim, Nanosim) is a plus.

3. Team oriented, love to work in young, international and highly motivated teams.

4. Good communication skills and High grade of flexibility.

5. Highly motivated and engaged.

6. Knowledge of Flash、SRAM and DRAM design is preferred.

7. English language skill in writing and speaking is a must.

5）数字前端设计工程师 Digital Front-End Design Engineer

Responsibilities:

1. Responsible for developing complex digital designs with emphasis on Front-End, including RTL Coding (verilog/VHDL) and top level integration.

2. Responsible for module/sub-system or system level simulation (modelsim, questasim  or NC-sim) and simulation flow optimization.

3. Develop module level specification and be able to finish the implementation with RTL code and simulation according to the module specification.

4. Responsible for the block constrains, and work as interface to help Back-end designer to implement the block APR.

5. Work as interface to check the APR performance with timing analysis (Prime-Time) and gate-level simulation.

Requirements:

1. Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2. Knowledge of SOC architectures and design flow, bus architectures, peripherals and so on is a plus.

3. Team oriented, love to work in young, international and highly motivated teams.

4. Good communication skills and High grade of flexibility.

5. Highly motivated and engaged.

6. Knowledge of Flash、SRAM and DRAM design is preferred.

7. English language skill in writing and speaking is a must.

8. Experience in Memory Controller design is a plus.

6）混合/模拟电路设计工程师 Mixed-signal/Analog IC Design Engineer

Responsibilities:

1. Design high-performance analog and mixed-signal circuits for consumer electronics applications.

2. CMOS circuit design for highly integrated dynamic memory devices, Memory Core, Sense Amplifier, Address decoder (Flash/SRAM/DRAM).

3. Check layout and physical implementation of the relative Block.

4. Circuit optimization and verification by simulations using HSPICE like simulation tools as well as event driven simulators

5. Other responsibilities include supporting other groups in the test, qualification and release to production.

Requirements:

1.      Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2.      Strong knowledge of Semiconductor Process and Device Physics.

3.      Strong set of Analog IC design skills in a wide range of circuits such as PLL/DLL, Band-Gap, IO (RCV/OCD/ODT), LDO, charge-PUMP and Active Filter.

4.      Knowledge of analog layout design and verification (DRC/LVS). Cadence, Synopsys and ICED layout tools experiences are preferable.

5.      Knowledge of software tools such as Schematic entry, HSPICE, Nanosim, etc. is needed.

6.      Good team player and communication skill in English.

7.      English language skill in writing and speaking is a must.

7） 混合电路设计工程师(存储器 IP)  Mixed-signal Design Engineer(memory IP)

Responsibilities:

 1. Responsible for high-performance  memory  IP design, verification, integration and test.

2. CMOS circuit design for highly integrated memory devices, Memory Core, Sense Amplifier, Address decoder (Flash/SRAM/DRAM).

3. Check layout and physical implementation.

4. Circuit optimization and verification by simulations using HSPICE , Nanosim, NC-Sim or other equivalent tools.

5. Support other teams in the IP test and qualification.

6. Support users in the IP integration and verification.

Requirements:

1.      Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2.  Knowledge of developing memory IP, especially SRAM IP.

3.  Knowledge of CAD tools such as Schematic entry, HSPICE, Nanosim, etc.

4.  Knowledge of layout design and verification (DRC/LVS)

5.  Knowledge of SoC design methodology and semiconductor process.

6.  High level of self-motivation and ability to be a good team player.  

7.  English language skill in writing and speaking is a must.

8） Layout Design Engineer版图设计工程师

Responsibilities:

1. Physical Design for Memory Products: Full custom Layout for analog and digital circuits in High performance DRAMs.

2. Floor planning signal- and bus planning according to predefined specifications.

3. Chip size optimization.

4. Area- and parasitic optimized layout.

5. Assembly of BLKs and top level hierarchies including routing.

6. Verification of circuits (Design Rule Check, Layout versus Schematic, Electrical rule check).

7. Generation of fill structures according to technology requirements.

8. Optical simulations on technology driven circuits.

9. Investigations on Electro migration and IR drop.

Requirements:

1.         Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2. Team oriented, love to work in young, international and highly motivated teams.

3. Good communication skills.

4. High grade of flexibility.

5. Highly motivated and engaged.

6. Knowledge of digital analog and/or mixture signal IC is preferred.

7. Knowledge of Flash、SRAM and DRAM design is preferred.

8. English language skill in writing and speaking is a must.

9） 集成电路测试工程师（设计分析与验证）

IC Product Test Engineer (Design Analysis and Verification)

Responsibilities:

1. Design verification and analysis of new Memory products.
2. Simulations and analyses together with responsible circuit designers, correlation of simulation-data versus measurement.
3. Hands on definition, programming and execution of test/test-flows on Memory analysis testers (V93k, HP95k, Mosaid).
4.Setting up engineering-environments specific to certain tasks and adjust set-up frequently, work with oscilloscopes, TDR, etc.

5. Perform electrical characterization of parameters specified in the data sheet

6. Verify functionality and performance of all DfT-features of a memory product, work with design and production test to identify problems
7.Support of (Field) Application Engineers to identify and analyze problems at the end-customer

8.Definition and specification for product-specific tester-hardware (load-boards, probe-cards, etc.)

Requirements:

1. Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2. Semiconductor device physics, circuit design and basic layout knowledge is a must.

3. Have Unix skills and Basic Programming skills (preferably C , Perl)

4. Interest to work in a lab-environment and do hands-on electrical measurements (memory-tester, oscilloscope, pico-probing, etc), setup and debug

5. High frequency measurement know how is desired.

6. Knowledge of DRAM test and analysis or DRAM tester programming (V93k, HP95k, Mosaid) is desirable.

7. Highly motivated and engaged, love to find tackle and solve new problems.

8. Good communication and presentation skills.

9. English language skill in writing and speaking is a must.

10）   电路设计工程师Circuit Design Engineer

Responsibility:

1.   Design and simulation of Flash memory at deep sub-micron process node including row and column decoding, read/program/erase control circuits and read sense amplifier etc.

2.   Verify the function and performance of FLASH memory at block-level and full-chip level.

3.   Floor-planning FLASH chip architecture.

4.   Work closely with layout engineer, provide layout guide line, and check the layout quality.

5.   Analysis chip's performance and debug chip's problems at silicon.

Requirements:

1. Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2.  Understand semiconductor device physics and deep sub-micron CMOS process.

3.  Understand digital and analog circuit theory very well.

4.  Knowledge of memory, esp. FLASH, circuit operation.

5.  Familiar with CAD tools for circuit simulation, e.g. HSPICE, NANOSIM and HSIM

6.  Must be able to learn quickly and work independently.

7.  Knowledge of FLASH design is preferred.

8.  1~3 years working experience is preferred.

11）SRAM IP 设计工程师SRAM IP Design Engineer

Responsibility:

1.      Floor-planning SRAM chip architecture.

2.      Design and simulation of SRAM decoding, read/write control circuits at block-level and full-chip level.

3.      Work closely with layout engineer, provide layout guide line, and check the layout quality.

4.      Analysis chip's performance and debug chip's problems at silicon.

5.      Familiar with SRAM IP design and test.

Requirements:

1.       Either Master or PhD in Microelectronics, Electronic Engineering, or related field.

2.      Understand semiconductor device physics and deep sub-micron CMOS process.

3.      Understand digital and analog circuit theory very well.

4.      Knowledge of memory, esp. FLASH, circuit operation.

5.      Familiar with CAD tools for circuit simulation, e.g. HSPICE, NANOSIM and HSIM

6.      Must be able to learn quickly and work independently.

7.      Knowledge of FLASH design is preferred.

8.      1~3 years working experience is preferred.

12）战略合作主管 Strategic Collaboration Executive

工作职责：

1.负责起草公司内外部所需材料（如项目报告等），办理各种项目申请手续及后续工作；
2.负责联系相关行业协会，政府职能相关部门和大学研究所等。建立长期良好沟通协调；
3.负责公司ISO9000质量认证和质量管理工作，负责公司运营主要性能参数的报告，数据分析，纠正措施直至实现；
4.由部门经理或总经理授权的其它工作。

岗位要求：

1.硕士研究生学历，微电子背景专业；
2.有较强的亲和力，沟通协调能力；
3.具有良好的文字功底，写作能力强；
4.良好的英文听、说、读、写、译能力；
5.良好的团队合作精神。

温馨提示：

·         简历中一定要注明应聘岗位， 学校，专业，学位， 生源地；

·         简历最好以附件形式发送，doc 或者pdf 格式均可；

·         简历一定要有英文版，而且最好中英文用一个文档，不要分成两个文件；

·         简历的最佳命名方式为名子_专业_学校_研究生/博士, 例如：李明_微电子_清华大学_研究生

·         申请多个职位可在Objective 中注明，但请勿重复发简历；

·         我们需要的专业：微电子学及其相关专业；（未在以上专业之列的你，如果觉得自己足够优秀，也可以发来简历试试看哦。）

·         请注明奖学金获得情况；

·         我们的工作地点是西安市。

联系方式：

·         公司地址：西安市高新区高新六路38号腾飞研发中心A座4楼

·         公司电话: 029-88318000 ext.8411（人力资源部）

·         传真:029-88453299

·         Email: hr-xian@

·         公司网址：ww***com[点击查看]