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飞思卡尔强芯集成电路设计有限公司实习生招聘信息
Position:
Analog Layout Engineer
Location: Tianjin
Job Description:
1. Perform full-custom layout, LVS/DRC physical verification and parasitic extraction for Freescale analog blocks and IO libraries.
2. Be responsible for generating all the physical views for chip level integration.
3. Communicate and get directions from the analog design engineers to ensure high quality.
Job Requirements:
1.Graduate students in Electrical Engineering Department
2.Be familiar with layout-related EDA tools, such as Virtuoso/Virtuoso XL from Cadence and Calibre DRC/LVS from Mentor Graphic
3.Knowledge on CMOS fabrication process and device structure is a plus
4.Knowledge on analog circuit design is a plus
5.Knowledge on ESD protection circuit is a plus
6.Understanding the importance of communication with analog designers
7.Good English skills (verbal and written)
8.Be interested in custom layout work and self-motivated
Contact Information:
Please understand that we will not reply your mail unless you are selected to enter the interview section, because there are so many resumes to be reviewed.
Please send your resume to mailbox:
Sunny Zhang (R62359@);
Taiya Ding (R64148@);
Antony Zhang(R65070@).
Position:
Analog Design Engineer
Job Description:
Analog circuit design, simulation, layout support and silicon validation. Support analog module integration.
Job Requirements:
1. Doctor or master degree of analog design or device engineering
2. Knowledge and skills on high speed/precision ADC/DAC, or low jitter clock modules, or power management cells …….is required.
3. Knowledge and experience on analog layout is required
4. Project experience on the above analog modules are highly preferred
5. Knowledge on CMOS device engineering is highly preferred
6. Good at communication in English
Jobsite: Suzhou
Please Send Resume To:
Robert Guo ( R61913@ )
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