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- 职位：
- 信息来源：清华大学
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Job Title: AE
Position Number: 1
Job Description:
- Solution development (firmware, algorithm, test, system, etc) of the industry lead touch related applications(Touchscreen or Trackpad)
- New feature and IP design and implementation on innovative touch related chips
- Provide reference designs/solutions in industry lead touch related solutions
- Key customers technical support.
- Work with marketing to exchange technical input on marketing collateral, new product definition, product features prioritization, customer feedback, and product training curriculum
- Work with IC design engineering to exchange technical support/sustaining engineering support, new product development interactions, impact of design limitations
Job Requirements:
- Solid “C” and assembly language familiarity
- Knowledgeable on analog and MCU based application design
- Experience on I2C, USB interface and other MCU on-chip external modules
- Fluent in English (both written and oral)
- Hard working and team player
- Takes initiative and sets high goals
- Customer service orientation
- Smart and confident
-projected capacitive technical experience is plus
Minimum Education & Work Experience:
- 2yrs embedded microcontroller (8-bit, 16bit)/embedded control application background
- Master Degree or above in EE/CE , including who will be graduated in 2013.
Job Title: ASIC Design Engineer
Location: Shanghai, China
Job Description:
As a logic designer, will be responsible for IP and full-chip RTL/logic design. He will be involved in all phases of the development, including spec definition, RTL coding, verification closure, synthesis, DFT, STA, etc.
Summary of Duties/Responsibilities:
Design Spec Definition: after get marketing requirement, be able to convert it into design spec with feature list, block diagram, input/output definition, performance analysis, die size estimation, etc.
IP design: be able conduct feasibility study, micro-architecture design, and RTL coding
Digital IC BE implementation: be able to run synthesis and DFT insertion tool with power aware constraints, need to analysis synthesis log and dft coverage using ATPG tool,
Will be involved in STA for timing sign-off,
Will work with verification engineer to setup verification plan, and debug for verification closure.
Job Requirements:
Fluent English skills
Hard working and team player
Takes initiative and sets high goals
Smart and confident
Self starter & ability to work in a team environment as an individual contributor
Track record of planning and delivering own work completely and on time
Education & Work Experience:
Master’s Degree or above in Microelectronics/EE/CE
Experience with Verilog logic design is a must
Experience with synthesis/sta tool is a must
Proficiency in one of script language, such as Perl, Tcl, will be a plus
Experience with logic verification will be a plus,
Knowledge of ARM CPU, AMBA bus, I2C/SPI/UART interface will be a plus,
Job Title: ASIC Verification Engineer
Location: Shanghai, China
Job Description:
Will be a member of logic verification team. Primary responsibility will be test bench development and verification of RTL logic designs. He will also be involved in the development of industry leading-edge OVM/UVM verification methodology for Cypress PSoC product
Summary of Duties/Responsibilities:
Requirements analysis. Must be able to effectively convert system and IC module specifications into written verification requirements (development of verification plans, detailed specifications, test bench functional requirements, test vectors, etc.)
Design of System-Verilog/OVM test benches for efficient and flexible use by self and others.
Verification of RTL logic designs and reporting of functional simulation and code coverage results.
Work with logic/RTL designers with debug efforts to achieve full functionality and code coverage metrics of IC designs.
Document test bench designs and participate in design reviews in accordance with department development process and company quality standards.
Test bench support, maintenance and user training.
Job Requirements:
Fluent English skills
Hard working and team player
Takes initiative and sets high goals
Smart and confident
Self-starter & ability to work in a team environment as an individual contributor
Education & Work Experience:
Master’s Degree or above in Microelectronics/EE/CE
Proficiency in one of script language, such as Perl, Tcl
Experience with Verilog logic design is a must
Experience with test bench development and behavioral functional model development is a must
Knowledge of ARM CPU, AMBA bus, I2C/SPI/UART interface will be a plus
Familiar with System-Verilog will be a big plus
Experience with VMM/OVM/UVM will be a big plus
