【开始时间：2013-11-06】 【结束时间：2013-12-31】
| 职位名称 | 工作地点 | 学历要求 | 招聘人数 | 操作 | |
| 1 | 数字集成电路后端设计工程师Digital IC Backend Design Engineer | 苏州 | 本科及以上 | 4 | |
Job Description:
1· Digital layout design for blocks and chips; 2· RTL synthesis and timing analysis; 3· Documentation of design procedures; 4· Work toward improving efficiency in design procedures and methodologies; 5· Communicate effectively with other team members. Requirements: | |||||
| 职位名称 | 工作地点 | 学历要求 | 招聘人数 | 操作 | |
| 2 | 数字集成电路前端设计工程师Digital IC Frontend Design Engineer | 苏州 | 本科及以上 | 4 | |
Description:
1. Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
2. Write RTL code for high-speed and multi-clock domain designs.
3. Perform functional verification of designs on block and chip level.
4. Perform synthesis and pre-layout timing closure.
5. Perform the clock domain crossing analysis for the different products lines.
6. Generate the Timing .lib and ATPG package for the different product lines.
7. Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
1. MSEE with 2 years.
2. Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
3. Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
4. Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
5. Understanding C and Perl programming.
6. Have a fluent oral and good writing English skill. | |||||
| 职位名称 | 工作地点 | 学历要求 | 招聘人数 | 操作 | |
| 3 | 数字集成电路前端验证工程师 Digital IC Frontend Verification Engineer | 苏州 | 本科及以上 | 4 | |
Description:
1.Develop and execute verification plan
2.Develop and maintain verification environment
3. Define and implement functional/code coverage plan
4.Functional/code coverage analysis
5.Run simulation for module and chip level, report and debug together with designer
6.Develop/maintain/enhance environment (TB/tools/scripts/flow)
Requirement:
1.MSEE with 2 years.
2.Proficient and experienced in SVA verification methodology
3.Experienced with hardware verification language (Vera, Systems, SystemVerilog)
4.Proficient with Verilog HDL
5.Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl
6.Familiar with ASIC design flow | |||||
