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职位描述：
Job Description
- Implement blocks in Verilog RTL
- Synthesize and close timing on the design
- Work closely with Design Verification team to review strategy, testplans and assist with debugs
- Work on code-coverage analysis, top-level connections, etc.
- Assist in lab bring-up, using logic-analyzer tools
Skills Required
- Ability to translate high-level functions into block designs
- Outstanding coding and scripting skills (Verilog, C, Perl). SystemVerilog is a plus.
- Demonstrated knowledge in FPGA/ASIC physical aspects (placement, routing, PLL, I/O, memories, etc.)
- Experience with industry tools for synthesis, timing analysis
- Outstanding written and spoken communication skills
- Well organized and Process oriented
- Knowledge of Ethernet is a plus
- Master degree is preferred.
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职位描述：
Job Description:
Participate in architecture and design verification of complex networking ASIC. Responsibilities include:
- Standalone and Integrated functional verification;
- Documentation and review of Verification architecture and testplans
- Develop verification environment (models, checkers, packet manager) using SystemVerilog
- Develop random, pseudo-random and directed tests
- Establish verification effectiveness using assertion/functional/code coverage and code reviews
- RTL and gates simulation, debug and root cause
- Regression triage and debug
- Formal verification and equivalence checking.
- Lab debug and design validation
Skills required:
- Prior significant verification experience on complex ASICs.
- Good background in networking concepts.
- Outstanding coding and scripting skills (Verilog, C, Perl). SystemVerilog is a plus.
- Chip and system and test experience.
- Good planning skills (well partioned designs, well organized code)
- Outstanding written and verbal communication skills
- Capability of critical thinking, challenging design intent
- Master degree is preferred.
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