职责范围:
As the ASIC Backend Engineer, you will be working closely with the front end ASIC team to synthesize the RTL, clean up the timing, go through the backend flows to deliver the tape-out.
背景要求
Strong understanding of backend ASIC design flow, go through synthesis, DFT, floor planning, clock tree synthesis, place and route, SI analysis, timing closure, LVS, DRC. Hands-on
A self-starter that is motivated and a good team player is expected.
BSEE required, MSEE preferred.
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