[上海]英伟达半导体技术服务上海）有限公司

一．公司简介

        NVIDIA (英伟达^TM)(：NVDA)是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000名员工，总部在加利福尼亚州圣克拉拉。

上海研发中心地址：上海申江路5709号（秋月路26号）矽岸国际2号楼

 

二．项目介绍

        自实习生作为校园招聘人才储备项目启动至今，每年都有几十名来自各大高校的优秀学生加入我们上海研发中心，与我们的员工一起参与到全球最先进视觉计算技术中，他们中的很多佼佼者已经作为应届生被录取成为NVIDIA正式员工。

 

 

三．投递方式

简历发送至HR(Yvette)邮箱:yvettes@；请将简历以及邮件主题命名为：姓名-申请职位-学校专业-毕业时间-周实习天数-实习月数（例如:张三-ASIC Physical Design-上海交大微电子-2016毕业-一周五天-12个月） (HR QQ:1992457940)

 

四．招聘岗位

1. ASIC-Physical Design Engineer (ASIC-后端实习生)

2. Embedded QA Software Engineer (嵌入式软件工程师)

3. System Design Software Engineer

 

职位详情欢迎私信~

 

五． 职位详述

1. ASIC-Physical Design Engineer (ASIC-后端实习生)

随着芯片工艺不断进步,设计规模的增大，对性能/功耗比期望的提高，数字芯片物理设计面临着高时钟，低功耗，多应用模式等巨大挑战。芯片的高效和高质量的物理实现是公司竞争力的保证。

作为NVIDIA的ASIC-PD工程师，你将负责从RTL冻结到流片这个阶段中综合，形式验证，约束文件制定，时序收敛以及相关方法学和工艺在时序方面影响的研究工作。在芯片实现方面，你将基于世界上最先进的流程面临最大的挑战。

工作职责:

-芯片集成，网表生成

-综合，网表质量分析

-逻辑等价性验证

-约束文件的创建和验证, 产生底层模块时序约束

-与前端工程师一起分析解决时序问题

-与P&R工程师合作完成芯片物理实现模块划分

-芯片级和模块级时序分析和时序收敛

-特殊工作模式的时序分析和时序收敛， 如IO，TEST等

-产生功能ECO脚本

-以上领域流程的开发，维护和增强

-以上领域方法的研究

职位要求:

-电子工程或相关专业硕士生或本科生

-有芯片设计经验

-有相关课程背景：电路设计，数字电路

-有相关EDA工具使用经验者优先：Synopsys (DC/PT/Formality), Cadence (RC/LEC)

-具有脚本编写能力者优先：Perl, TCL

-良好的英语交流能力

 

 

2. Embedded QA Software Engineer (嵌入式软件工程师)

Qualifications:

The candiate will take the responsibilty to test our sotware distirbutions that includes mobile/embedded OS, SDK, compilers and samples codes.

 

Responsibilities:

 

- Strong knowledge on Windows and Linux Operating systems

- Knowledge on build tools like Make and ant

- Strong at scripting, like perl , shell and batch scripting.

- Good debugging skills and analysis skills on installations and builds

- Good hands on about Strong analysis skills on system / product configurations and setups.

- Added advantage with C,C++ and Java languages

- Added advantage with experience using QT

 

3. System Design Software Engineer

Responsibilities:

- We are looking for world class engineers to design, model, analyze and verify next generations of GPU architecture.

- The candidates will work with a group of architects to design and develop proprietary internal tools for the visualization, analysis, and debug and verification of tests and applications on various functional and performance simulations of future chips.

- The candidates will have opportunities to get involved in cutting-edge GPU macro- and micro-architecture design, verification and optimization, including porting commercial applications to test benches, identifying performance hotspots and data mining for performance analysis.

 

Requirements:

- Bachelor Degree or higher majoring in CS/EE/Mathematics or relevant fields.

- Solid computer science background

- Strong C/C++ programming ability.

- Excellent English writing for engineering documentation, English oral well enough to attend meetings.

- Experience in the following areas is a plus:

- Scripting language (Perl, Python, Ruby) experience is a plus.

- 3D graphics (D3D or OpenGL) application development.

- Parallel computing/CUDA/OpenCL/HPC development.

- Microprocessor architecture design & verification.

- System level programming experience in OS, compiler, driver, tools, virtual memory system, etc.

- Multimedia (video, image processing, visualization) application development

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