- 工作地点：其它
- 职位：
- 信息来源：安徽大学
说明：
此信息由安徽大学审核并发布（查看原发布网址），应届生求职网转载该信息只是出于传递更多就业招聘信息，促进大学生就业的目的。如您对此转载信息有疑义，请与原信息发布者安徽大学核实，并请同时联系本站处理该转载信息。
About Silego
• Founded in 2001
• Four Product Lines with over 200 Products
• World-Class manufacturing
Foundries: TSMC, Vanguard
Packaging: ASE, Chip MOS, SPIL, SPEL
• Five Global Centers
Corporate HQ: Santa Clara, CA
Design Centers: USA, Korea, China
Operation Teams: USA, Taiwan
Sales and Apps Support: Global
关于Silego
•成立于2001年
•四个产品系列200多个产品
•世界级的制造
铸造：TSMC, Vanguard
包装：ASE, Chip MOS, SPIL, SPEL
•全球五大中心
公司总部：美国加州圣克拉拉，
设计中心：美国，韩国，中国
操作团队：美国，中国台湾
销售和应用服务支持：全球
Silego Technology, Inc. recognized with the Deloitte Technology Fast 50 Rising Star ranking as one of the fastest growing technology companies in the Silicon Valley. Silego develops silicon solutions to reduce part count, power, and cost and is one of the fastest growing semiconductor companies in the Silicon Valley.
Silego is the world’s largest notebook and netbook clock supplier and has numerous product lines that cover DDR3 register ICs, Consumer ICs, Notebook and Netbook ICs. Silego is headquartered from Santa Clara, California with operations and design centers around the globe. Silego Technology is privately owned and backed by leading venture capital firms.
Silego被德勤认为是在硅谷发展迅猛的前50的科技公司之一。Silego开发硅芯片解决方案，以减少元件数量，功耗和成本，是在硅谷增长最快的半导体公司之一。
Silego是全球最大的笔记本电脑和上网本时钟供应商，拥有大量的产品线，涵盖DDR3寄存器集成电路，消费性产品，笔记本电脑和上网本芯片。 Silego总部位于加利福尼亚州圣克拉拉，其业务和设计中心遍及全球。Silego科技是一家私人持有的并获得领先的风险投资公司支持的公司。
Job Description:
This position will participate in layout design team for analog and mixed signal circuits on CMOS process. Work through entire chip construction process, from preliminary floor planning, detailed sub-block layout, and global placement and routing. Responsible for running full verification sequence using advanced EDA tools. The responsibilities will include but not limited to:
Layout floor planning of large, mixed signal IC
Transistor level sub-block layout based on schematics provide by designers, including careful analog considerations
Verifying and completing the IC with DRC/LVS checks, chip-finishing and bonding
Delivering back-annotated data needed for timing verification of modules, both standalone and embedded in top level circuitry
Job Requirement:
BSEE or above, MSEE preferred
Be able to translate circuits schematics directly to layout
Understand IC process basics
Understand circuit basics and how they impact IC layout strategy
Very good communication skills in English and Chinese
工作地点：合肥
工作经验：应届毕业生
最低学历：本科
管理经验：否
专业要求：微电子相关专业（应用物理 电子科学与技术 微电子学）
工作性质：全职
招聘人数：1人
联系方式：0551-65368431，简历请投至 xli@
公司名称：Silego Technology,Inc.
公司地址：安徽省合肥市天元路3号留学生园2号楼303
公司主页：ww***com[点击查看]
薪资福利：年薪8万左右，五险一金，双休
责任编辑：管理员02
