
此信息由前程无忧(51JOB)审核并发布(查看原发布网址),应届生求职网转载该信息只是出于传递更多就业招聘信息,促进大学生就业的目的。如您对此转载信息有疑义,请与原信息发布者前程无忧(51JOB)核实,并请同时联系本站处理该转载信息。
Responsibilities 岗位职责:
-Work closely with SoC team (architechts, logic designers, etc) for chip/block level physical designs.
-Responsible for low power SoC design with embedded analog, memories, and RF IP blocks.
-Chip and block level low power definition, RTL synthesis, logic/power equivalent check, clock tree synthesis, P&R, STA/timing noise closure, etc.
-Responsible for die size estimation, power distribution planning, floor-plan and power (static and dynamic) analysis.
-Responsible for chip-finishing, DFM, DRC/LVS physical verification.
Requirements 任职要求:
-Bachelor, Master or above on Electronics, Communications, Microelectronics Engineering, Computer Science or related majors.
-Experienced on high-level RTL languages with good knowledge of IC design flow, including coding, simulation, verification, synthesis, DFT and STA.
-Familiar with the main EDA tools, such as Cadence, Synopsys and Mentor, and their related methodology/flow.
-Familiar with high speed serial bus, graphic, audio/video, or display/sensor such as USB/PCIe/HDMI/MIPI/GPU is a plus.
-DDR knowledge and experiences is a plus.
-Familiar with AMBA(AXI/AHB/APB, etc.) specs is a plus.
-Scripting language like Perl, Tcl or Python experiences is a plus.
-Have knowledge about computer architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer is a plus.
-Prefer experience of formal verification with property scheme, for example SVA (System Verilog Assertion).