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Analog Layout Engineer
Department: Central Engineering
Job Description:
Be a part of the Central Engineering IP team at Marvell china. Main responsibility is perform analog layout and related drc/lvs/erc/ant verification, debugging and violations fix. Will be responsible for all levels of analog layout from block level up to the IP/AFE most top level integration and physical verification. You will communicate and get directions from experienced analog design engineers and analog layout engineers to guarantee high quality.
Job Qualifications:
BS degree, major in electronic engineering, computer science, or equivalent.
Good communication skills in written and spoken English.
Good team work and communication skills. Hardworking and self-motivated under a high competition design/layout team.
Understanding basic characteristic of transistor, resistor, capacitor and diode.
Understanding of layout impact on device matching, noise coupling from signal, supply and substrate.
Understanding the importance of signal flow, power/ground structure and block placement in layout floorplan.
Experience with unix/linux, cadence virtuoso, synopsys laker is plus.
Experience with calibre drc/lvs is plus.