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Department: Storage
Description:
Worktogether with algorithm team and design team to develop testplan and testcasefor various blocks in our Read Channel products.
Maintainand help improve our UVM based verification environment.
Improveour verification coverage and reduce number of tape out.
Researchon some advanced verification technology such as assertion based formalverification.
Qualifications
Majorin EE, CS or related.
Familiarwith Verilog and RTL design
Familiarwith System-Verilog and UVM verification methodology
Familiarwith script languages(perl,tcl,sh etc.) is a plus
Familiarwith digital signal processing knowledge is a plus
Goodproblem solving and communication skills