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Description
- IC design implementation from RTL to netlist including synthesis, timing constraint composing, timing eco, design for test
- IC physical implementation from netlist to GDSII, including floor planning, power grid implementation, place and route, clock tree synthesis, timing eco, design closure, flip-chip design
- IC design verification including timing analysis, timing signoff, formal verification and low power verification.
- IC physical verification including physical verification, crosstalk analysis, power analysis, ESD analysis, EM analysis.
- Program development in TCL or Perl to improve productivity.
- You will have the opportunity to develop next generation IC implementation flow for the most advance technology.
- As a member of central IC design team, you will play an important role to assist multiple Marvell’s business unit with
challenge of different physical design jobs.
Qualifications
- BS or MS in EE or CS from a good university, major in VLSI, logic or CPU design. Good GPA preferred.
- Detail oriented, self-motivated and team player. Good verbal and written communication skills.
- To qualify for the job, you should have some of the following technical background:
? Working knowledge of HDL, such as Verilog, frontend design or SOC integration experience, including synthesis, timing
analysis and timing constraint creation. Experience in Design-for-test (DFT), with JTAG, BIST and SCAN.
? Working knowledge of LEF/DEF and backend physical design, such as floorplanning, standard cell placement and
routing or layout integration.
? Understanding of SPICE model and transistor circuits, and standard cell layouts.
? IC design methodologies using design automation EDA tools, ASIC design flow, and deep sub-micron technology
issues.
? Familiarization with scripting programming, such as Tcl or Perl. Experience with makefile and understanding of the
design automation for efficiency.
? Working experience with any of the EDA tools listed below:
ü Synopsys: JupiterXT, Physical Compiler, IC Compiler, StartRC, PrimeTime, PT-SI, PrimeRail, Formality, Hercules,
Design Compiler, TetraMAX)
ü Cadence: EDI, Innovus, Genus, Quantus, Tempus, Conformal, Voltus
ü Mentor: Calibre, TestKompress, FastScan, Olympus
ü Ansys: Apache Redhawk