
此信息由前程无忧(51JOB)审核并发布(查看原发布网址),应届生求职网转载该信息只是出于传递更多就业招聘信息,促进大学生就业的目的。如您对此转载信息有疑义,请与原信息发布者前程无忧(51JOB)核实,并请同时联系本站处理该转载信息。
Position Description:
Develop, enhance and maintain digital mixed signal simulator which supports the co-sim between different HDL languages, such as Verilog, VHDL, SystemVerilog, etc, with some direction from manager or senior engineers
Position Requirements:
1. Familiar with Verilog, VHDL, SystemVerilog language
2. Analog circuit or digital simulator development experiences
3. Skilled in C/C++ programming, familiar with development under Linux/Unix environment.
4. Being familiar with Real number modeling is a plus
5. Being familiar with Digital Mixed-signal design is a plus
6. Being familiar with low power design is a plus
要求:每周工作4天以上,持续至少6个月以上,硕士相关专业2019年及以后毕业
主题格式:姓名-BJ Intern-学历-学校-毕业年份
投递邮箱:job_china@