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Job Description
Become a member of a world-class analog design team in providing high performance analog and mixed mode circuits for leading data communications and networking products, in 1gig and 10gig data rate. Designers have opportunities to design high performance analog-to-digital converters (ADC), digital-to-analog converters (DAC), filter, adaptive equalizers, clock and data recovery (CDR) circuits, and phase-locked loop (PLL) or other timing circuits. Team members participate in circuit architecture, circuit implementation, design review, layout, and silicon validation.
Qualification
– High performance CMOS analog design experience for communications
– Design experience in analog-to-digital converter (ADC), including but not limited to flash, 2-step (sub-ranging, folding), pipeline, cyclic, sigma delta, and other techniques.
– Design experience in digital-to-analog converter (DAC) for driving high precision output, such a 50ohm line driver.
– Design experience in filters and/or equalization, including but not limited to continuous time filter, discrete-time filters, finite-impulse response (FIR) filter, or decision-feedback equalizer (DFE).
– Design experience in Serdes and timing circuits such as PLL, CDR, TX and RX functions.
– Design experience in other analog functions is a plus, such as bandgap, regulator, crystal oscillator, etc.
– Knowledge in signal processing and communication theories is a plus.