
此信息由前程无忧(51JOB)审核并发布(查看原发布网址),应届生求职网转载该信息只是出于传递更多就业招聘信息,促进大学生就业的目的。如您对此转载信息有疑义,请与原信息发布者前程无忧(51JOB)核实,并请同时联系本站处理该转载信息。
Job Description
Candidates will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign- off. Candidates will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests.
RTL implementation base on design specification;
Setup and maintain frontend flow, e.g. Lint, CDC, LEC and Synthesis;
Co- work with verification/validation team on design failure;
Co- work with backend team on timing closures and P&R;
Design document writing and maintain.
Qualification
BS/MS in EE
Enrolled in the master's degree course related to ASIC development
Experience with digital design, running EDA tools of simulation and running frontend flow
Good communication skills and willing to learn