职位描述 |
Performance Objectives:
The Successful Candidate will:
? Drawing layout of semiconductor valid/non-valid devices for test patterns/chips.
? Perform DRC & LVS verification on all test pattern/chip layouts
? Perform floor-planning for production and development test patterns.
? Perform device matching, and other specialized layout techniques.
? Write automation scripts for basic layout functions.
? Demonstrates excellent written and verbal communication skills required to effectively interface with other engineers and management.
Skills/Experience required:
Required Qualifications:
? BS Degree in Electrical Engineering or related field plus 0-2 years of experience.
? Demonstrated programming skills in one or more of the following: C/C , Java, or Perl
? Demonstrated knowledge of using layout design tools such as Cadence or Mentor.
? Excellent technical communication skills.
? Strong English communication capability
? Strong learning capability
? Good team player
Preferred Qualification:
? Familiar with semiconductor manufacturing processes. Basic Process and Device technology experience.
? Demonstrated skills/knowledge of design revision control systems such as Cliosoft, Synchronicity or ICManage.
? Advanced EDA flows and tools: Circuit simulations and Verification
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