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Responsibilities:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
Focus on physical design of deep sub-micron chips including block level (full chip) floor planning, cts, place & route, timing closure, physical verification etc.
Requirements:
MS major in EE or related.
Familiar with general IC design flow, familiar with physical design flow and EDA tool (Synopsys or Cadence) is a plus.
Familiar with Linux, skill in scripts including perl/tcl/cshell/python is a plus.
Good communication skills, proactive and team work.
Good spoken and written English.