ASIC Design & EDA Software Engineer

标 题: ASIC Design & EDA Software Engineer
发信站: 水木社区 (Mon Oct 30 19:42:57 2006), 站内

Company Introduction:
Agate Logic is a global pioneer of the innovative configurable system-on-chip (SoC) technologies. The company offers a full spectrum of SoC devices, software design tools, intellectual property (IP), and design services.

Agate Logic is headquartered in U.S.A., and is currently hiring engineering and field support talents in its new Beijing R&D center.

　　
Agate Logic 致力于可配置系统芯片的开发与销售，采用本土化的芯片制造商，目标定位于多种应用类市场领域，例如通信设备、工业控制系统、消费类电子产品等。我们的产品以可配置、可编程、多功能为特点，提供了一个通用的设计平台，可以运用于任何领域。我们的通用芯片平台，高效的EDA软件加上可配置的IP模块，能为系统提供商带来更多的便利。

Agate Logic是全球领先的CSoC芯片设计公司，公司总部位于美国加州，由几位留美博士共同创立，已有超过五年的历史。现在致力于发展中国的业务，推动中国本土芯片产业的发展，分别在北京和上海设立了研发和销售中心。Agate Logic北京研发中心现位于中关村科技园区清华科技园内。

Agate Logic在北京成立的研发中心是我们的一项重要战略，吸纳优秀的软件和硬件技术人才是确保我公司保持健康成长的关键。我们迫切需要拥有各类技术的优秀工程师加盟我公司。

地址：北京海淀区清华大学清华科技园
E-mail: hr@

Job Titles:
- IC Back-end Designer IC后端设计工程师 (1 position)
- IC Circuit Designer IC电路设计工程师 (1 position)
- Senior EDA Software Engineer / Project Manager 资深EDA软件工程师 / 项目经理 (1 position)
- EDA Software Engineer EDA软件工程师 (4 positions)
- Software GUI Engineer GUI软件工程师 (1 position)
- Software Release Engineer 软件发布工程师 (1 position)
- Embedded Software Engineer 嵌入式软件工程师 (2 positions)
- Senior Hardware IP Design Engineer / Project Manager 资深硬件IP设计工程师 / 项目经理 (1 position)
- Hardware IP Design Engineer 硬件IP设计工程师 (1 position)
- Application Design Engineer 应用设计工程师 (2 positions)
- Senior QA Engineer / QA Manager 质量经理 (1 position)
- Verification Engineer 验证工程师 (1 position)
- Front-end ASIC design Engineer 前端ASIC设计工程师 (1 position)
- Field Application Engineer 现场应用工程师 (2 positions)


Job Title: IC Back-end Designer IC后端设计工程师 (1 position)
Job Responsibilities:
- Responsible for developing, and verifying complex digital designs with an emphasis on backend tasks of automated and manual placement and timing closure.
- Develops tool flows and scripts to automate the implementation of complex digital functions.
- Works with RTL designer to best optimize the physical design implementation, and minimizes timing closure risks. Assignments are given in the form of objectives.
- Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.
- Expected to analyze project areas, refine problem descriptions, and develop novel technical solutions.
- Designs and implements sophisticated algorithms to solve complex problems.
- Write paper for technical conferences.
- Company expert in the area of APR and backend digital design.
Requirements:
- BS in EE/CS with 3+ years of relevant experience, MS with 2+ years of relevant experience, or related Ph.D. with 1+ years of experience in digital back-end design.
- The individual should have experience with several APR tools, timing tools, parasitic extraction methods, standard cell library timing models, and scripting languages.
- It is essential that the individual has strong desires to learn and explore new technologies and are able to demonstrate good analysis and problem solving skills.
- Prior knowledge and experience of CAD tool development are required. Prior experience with primetime and Astro would be beneficial.

Job Title: IC Circuit Designer IC电路设计工程师 (1 position)
Job Responsibilities:
Responsible for full-custom circuit implementation, debug, schematic entry, simulations, layout supervision and bench characterization.
Requirements:
- MSEE with at least 2 years of CMOS circuit design experience.
- Familiar with usage of major EDA tools: Composer, Hspice and Hsim. Hands-on experience on basic LAB equipments is necessary.
- Highly motivated to complete assignment in a dynamic working environment.
- Must be a good team player with excellent communication skill in both Mandarin and English.
- Experience on PLL and High Speed IO designs is a plus.

Job Title: Senior EDA Software Engineer / Project Manager 资深EDA软件工程师 / 项目经理 (1 position)
Job Responsibilities:
Independently specify, design, implement, and test software components as parts of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- Ph.D., M.S. with at least 3 years of experience, or B.S. with 5 years of experience in related areas
- Have at least 2 years of experience in EDA software development with solid understanding in at least one area of EDA algorithms
- Excellent programming skills in object-oriented design, C++.
Preferences:
- Knowledge of algorithms used in logic synthesis, technology mapping, placement, routing, timing models and analysis, and/or FPGA architectures.
- Familiarity with shell scripts, Python, Perl and/or Tcl.

Job Title: EDA Software Engineer EDA软件工程师 (4 positions)
Job Responsibilities:
With help from senior staff, specify, design, implement, and test software components as parts of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- M.S., or B.S. with 2 years of experience in related areas
- Have at least 1 year of experience in software development with talents in algorithm design
- Excellent programming skills in object-oriented design, C++.
Preferences:
- Education and experience with algorithms used in logic synthesis, technology mapping, placement, routing, timing models and analysis, and/or FPGA architectures.
- Course work in combinatorics
- Familiarity with Java, shell scripts, Python, Perl and/or Tcl.

Job Title: Software GUI Engineer GUI软件工程师 (1 position)
Job Responsibilities:
With help from senior staff, specify, design, implement, and test software components as parts of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- M.S., or B.S. with 2 years of experience in related areas
- Have at least 1 year of experience in software development with talents in graphical user interface design
- Excellent programming skills in object-oriented design, C++.
Preferences:
- Familiarity with Qt, MFC and Java
- Skillful in shell scripts, Python, and/or Perl.

Job Title: Software Release Engineer 软件发布工程师 (1 position)
Job Responsibilities:
- Setup and maintain the software development environment for version control, build, debug, regression test, and product release.
- Help define and execute large-scale performance evaluation experiments on networks of computers.
Requirements:
- MS or BS with at least 2 years of experience
- Excellent written and verbal communication skills.
- Skillful in using GNU compiler tool chains including gcc and make, and various scripting languages, such as csh, bash, python, and perl.
- Computer network administration experience
- Skillful in C, C++, shell scripts, Python, and/or Perl.
- Experience with Windows and Linux.
- Computer network administration experience.
Preferences:
- Solid working knowledge of object-oriented design, C, C++ and Java

Job Title: Embedded Software Engineer 嵌入式软件工程师 (2 positions)
Job Responsibilities:
- Specify, design, implement and test software tools for downloading bitstreams to and debugging of configurable logic devices and associated memory and peripheral devices.
- Also work on embedded MCU to interface with third-party compiler, debugger and programming tool chain.
Requirements:
- MS, or BS with at least 2 years of experience
- Solid working knowledge of C, C++
- Experience with RTOS, including Linux, uClinux and/or VxWorks.
Preferences:
- Experience with writing Flash memory device drivers
- Experience with using and writing Microsoft Windows XP device drivers, including USB and parallel ports
- Experience with using and writing Linux device drivers, including USB and parallel ports
- Familiarity with writing drivers for SPI, I2C, UART.

Job Title: Senior Hardware IP Design Engineer / Project Manager 资深硬件IP设计工程师 / 项目经理 (1 position)
Job Responsibilities:
Independently specify, design, implement, verify and document hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- Ph.D., M.S. with at least 3 years of experience, or B.S. with 5 years of experience in related areas
- Have at least 2 years of experience in processor, memory controller, PCI, or networking equipment design
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 2 years
- Good programming skills in C.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Familiarity with Synopsys Design Compiler, ModelSim, Prime Time.
- Skillful in C, C++, shell scripts, Python, and/or Perl.

Job Title: Hardware IP Design Engineer 硬件IP设计工程师 (1 position)
Job Responsibilities:
With help from senior staff, specify, design, implement, verify and document hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- M.S. or B.S. with at least 2 years of relevant experience.
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 1 year
- Good programming skills in C.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Familiarity with Synopsys Design Compiler, ModelSim, PrimeTime.
- Skillful in C, C++, shell scripts, Python, and/or Perl.

Job Title: Application Design Engineer 应用设计工程师 (2 positions)
Job Responsibilities:
- Responsible for providing support for customers logic and/or system design using Agate devices.
- Supporting in-depth technical inquiries, providing design evaluations and recommendations, and creating technical collaterals including documentation, design examples and demos.
- Working with the development teams to provide feedback to improve Agate’s design tools and methodology. Seniority depends on levels of experience.
Requirements:
- M.S. or B.S. with at least 2 years of experience in related areas
- Have at least 2 years of FPGA design experience in using Altera Quartus II or Xilinx ISE.
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 1 years
- Good programming skills in C.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Skillful in high-speed board level system design.
- Familiarity with Synopsys Design Compiler and Synplicity.
- Skillful in C, C++, shell scripts, Python, and/or Perl.

Job Title: QA Manager / Senior QA Engineer 质量经理 / 资深质量工程师 (1 position)
Job Responsibilities:
In charge of the quality assurance process in delivering a state-of-the-art EDA design software tool
Requirements:
- Ability to plan and execute software quality assurance activities for
a software system on various platforms, including Windows and Linux
- Experience in software delivery processes, including build and release
- Programming experience in C, C++, csh, python, perl and tcl
- MSEE or MSCS with at least 3 years of experience in related areas
- Familiar with Visual C++, gcc and make
- Familiar with bug tracking tools, such as Bugzilla
- Have excellent analytical skills, effective prioritization and problem solving skills and demonstrated ability to execute and achieved desired results
- Extremely detailed oriented
- Very comfortable working in a team environment
- Disciplined, self-motivated and patient
- Excellent communication and presentation skills
- Excellent inter-personal communication skills
- Fluent in reading and writing English

Job Title: Verification Engineer 验证工程师 (1 position)
Job Responsibilities:
To do the whole chip function verification and gate-level net list verification.
Requirements:
- Bachelor in E.E. with 2 to 3 years or Master in E.E. with 1 to 2 years of SoC verification experience.
- Hands in HDL RTL coding, and Assertion-based verification methods;
- Familiar with and related EDA tools (such as VCS +Vera, Questa) ;
Preferences:
- shell script(csh, tcl or perl)
- Familiar with C, system-verilog language
- Familiar with FPGA

Job Title: Front-end ASIC design Engineer 前端ASIC设计工程师 (1 position)
Job Responsibilities:
To do digital IC/ASIC design, synthesis, Static Timing Analysis
Requirements:
- Bachelor in E.E. with 2 to 3 years or Master in E.E. with 1 to 2 years of ASIC/SoC design experience.
- Hands on in HDL RTL coding, shell script(csh, tcl or perl),
- Familiar with Front-end Flow, logic synthesis using Synopsys\' Design Compiler, Timing check with PrimeTime, Test bench development and Verifications and Design-for-test scan insertion.
Preferences:
- Familiar with popular MCU, such as 8051, MIPS or ARM
- Familiar with C, system-verilog language
- Familiar with FPGA

Job Title: Field Application Engineer 现场应用工程师 (2 positions)
Job Responsibilities:
- Responsible for providing support for customers logic and/or system design using Agate devices.
- Supporting in-depth technical inquiries, providing design evaluations and recommendations, and creating technical collaterals including documentation, design examples and demos.
- Working with the development teams to provide feedback to improve Agate’s design tools and methodology. Seniority depends on levels of experience.
Requirements:
- M.S. or B.S. with at least 2 years of experience in related areas
- Have at least 2 years of FPGA design experience in using Altera Quartus II or Xilinx ISE.
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 1 years
- Good communication skill.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Familiarity with Synopsys Design Compiler and Synplicity.

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