Cisco：VoIP softswitch developer/ ASIC Design Eng

发信人: hulu(葫芦－－小猴爱大猪更爱小猴), 信区: job
标  题: Cisco：VoIP softswitch developer/ ASIC Design Eng
发信站: 饮水思源 (2006年10月30日22:55:34 星期一)

Job Title: Hardware Engineer (ASIC/FPGA Design Engineer)

Note:
- The job description below is for a Senior ASIC/FPGA Design Engineer
- For junior engineer, requirements are less strict    
- Looking for
o 2 Senior ASIC/FPGA Design Engineer, and
o 3 ASIC/FPGA Design Engineer

Job Description
- Fully define an FPGA/ASIC design based on high-level functional requirements

- Document and review top-level and block architectures
- Implement blocks in Verilog RTL
- Synthesize and close timing on the design
- Work closely with Design Verification team to review strategy, testplans and
 assist with debugs
- Work on code-coverage analysis, top-level connections, etc.
- For FPGA designs, perform back-end placement and routing
- Assist in lab bring-up, using logic-analyzer tools
- Adherence to process and sound methodology

Skills Required
- 7+ years experience in FPGA and/or ASIC logic design
- Ability to translate high-level functions into block designs
- Outstanding coding and scripting skills (Verilog, C, Perl)
- Demonstrated knowledge in FPGA/ASIC physical aspects (placement, routing, PL
L, I/O, memories, etc.)
- Experience with industry tools for synthesis, timing analysis
- Outstanding written and spoken communication skills
- Experience in mentoring junior designers
- Well organized and Process oriented
- Knowledge of Ethernet is a plus

Educational Background
Requires MSEE/CS combined with 5+ years of related experience or BSEE/CS combi
ned with 7+ yrs related experience.

Job Title:  Hardware Engineer (ASIC/FPGA Design Verification Engineer)

Note:
- The job description below is for a Senior ASIC/FPGA Design Verification Engi
neer
- For junior engineer, requirements are less strict
- Looking for
o 3 Senior ASIC/FPGA Design Verification Engineer
o 6 ASIC/FPGA Design Verification Engineer

Job Description:
Participate in architecture and design verification of complex networking ASIC
.  Responsibilities include:
- Architecture/Micro-Architecture definition
- Standalone and Integrated functional verification;
- Documentation and review of Verification architecture and testplans
- Develop verification environment (models, checkers, packet manager) using Sp
ecman/Vera
- Develop random, pseudo-random and directed tests
- Establish verification effectiveness using assertion/functional/code coverag
e and code reviews
- RTL and gates simulation, debug and root cause
- Regression triage and debug
- Formal verification and equivalence checking.
- Lab debug and design validation

Skills required:
- Prior significant verification experience on complex ASICs. 
- Good background in networking concepts. 
- Experience with Vera/Specman and Verilog. 
- Chip and system and test experience. 
- Programming and scripting skills.
- Good planning skills (well partioned designs, well organized code)
- Outstanding written and verbal communication skills
- Capability of critical thinking, challenging design intent

Education:
MSEE with 5+ yrs or BSEE/CS  with 7+ yrs relevant experience

 

 

 

. 
Job Title:  HW Engineer (System Board Design Engineer)

Note:
- The job description below is for a Senior System Board Design Engineer
- Looking for
o 1 Senior System Board Design Engineer
o 3 System Board Design Engineer

Job Description:
- Participates on a project team of engineers involved in the specification, d
esign, development and test of hardware for leading core routing products.
- Design hardware solutions and work in the team to develop boards.
- Participate in definition, design, and debug of GSR next-generation SP produ
cts.
- Works under department strategy and direction.
- Translates department goals into own work assignments.
- Independently determines and develops approach to solutions.
- Work is reviewed upon completion for adequacy in meeting objectives.
- Interfaces cross-functionally at the working team level.
- Work under direction of the project leader with ASIC and Mechanical Engineer
ing, Diagnostic and Software teams to define features and participate in probl
em resolution.
- Work closely with diagnostics and software developers throughout the develop
ment process.
- Job involves set up and monitoring EDVT units.

Skills required:
- Prefer experience in embedded CPUs,  memory architectures, and FPGA technolo
gy.
- Experience with DVT process is critical.
- Experience with, FPGA simulation or design verification techniques are all a
 plus.
- Requires excellent communication skills.
- Mentors junior team members.
- Tackles complex issues in creative ways.
- Problem solving requires originality and ingenuity using knowledge gained wh
ile specializing in field.
- Self motivation, teamwork and strong communication skills are essential
- Additional skills would be having the capability of proficiency with spice (
or equivalent) circuit simulation, field-solver and time/frequency domain anal
ysis, familiarity with high speed serdes design, PLL design and LVDS, LVPECL,
CML and other high-performance I/O technologies.
- Experience correlating simulation results with lab measurements using oscill
oscopes, TDRs and spectrum analyzers is a plus.

Education:
MSEE with 5+ yrs or BSEE/CS  with 7+ yrs relevant experience

PGW Developer
JD
Participate (may take on a lead role) on a project team of engineers involved
in development of software for Cisco products.  Requires use of a strong backg
round in SW design, documentation and implementation, on projects that may inc
lude any of the following list of responsibilities:  Design applications invol
ving multi-platforms.  Design and develop new software product features.  Repr
esent Cisco to customers and the rest of the industry in the development and d
eployment of internetworking solutions.  Contribute innovative ideas for multi
ple module architecture.  Define product internal/external interfaces.  Develo
p complex, multiple modules of code independently.  Write complete functional
and design specs independently.  Write portions of product spec.  Lead develop
ment of subsystems.  Contribute to the development of project goals, schedules
, and resource planning.  Develop automated test plans.  Perform complex syste
m level tests.  Interface with other functional groups (EQA, Manufacturing, etc.)  Evaluate and recommend tools.  Solves complex problems at
the system level.  Define product level test and simulation strategy.  Partici
pate in Cisco's Patent Program.
 
This is for a position in the PGW 2200 development team.  The PGW 2200 is a Vo
IP softswitch that performs signaling and call-control tasks, including routin
g voice and data calls between the PSTN and VoIP networks.  More information o
n the PGW 2200 can be found at:
ww***com[点击查看]
 

Education:
Typically requires MSEE/CS combined with 3-4 years of related experience, or B
SEE/CS combined with 4-7+ yrs related experience.

Skill needed:
1. Development experience using C++, good understanding of object oriented pro
gramming.
2. Previous experience of developing products on Solaris/Linux platforms.
3. Experience with SS7 PSTN is preferred.
4. Knowledge of VoIP protocols is preferred.
 
If you are interested and confident, please send your resume in English to: st
ephan_lu2000@yahoo.com.cn.
Please do not send message or email to this bbs account.
If you have any questions, please feel free to contact me.
PS: This is Cisco regular recruitment, not the campus recruitment.