ST意法半导体招聘

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发信人: sary (0000), 信区: Job
标  题: ST意法半导体招聘
发信站: 日月光华 (2006年11月20日19:26:59 星期一), 站内信件

勿投条

Title: Layout Engineer
Work Location: Shanghai
No.: 5
Email : recruit1.sh@
Responsibilities:
-To translate the electrical schematics into their physical layout, using 
ST's processes
and their associated design rules;
-To prepare preliminary floor plan with the design engineer and estimate 
the die size;
-To prepare bonding diagram and run assembly rule check;
-To carry out DRC, LVS rule checks and design/layout reviews;
-To extract parasitic devices for post-layout simulations.
Requirements:
-Bachelor degree in Electronics Engineering;
-Proficient in major CAD tools and software.
Please use “Application for Layout engineer” as Email subject

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