职位描述：
工作要求：
具有良好理论基础的应届和最近的毕业生。
电子工程或相关专业硕士以上学历，一年以上的FPGA 或 ASIC设计工作经验。
具有良好的FPGA 或 ASIC设计技术背景，包括 RTL 编程，仿真，综合和静态时序分析能力。
必须熟练掌握 Verilog 编程，以及拥有良好的脚本，例如perl和tcl等，的编写能力。
良好的写作及口头交际能力，英语听、说、读、写熟练。
良好的团队合作精神。
工作描述：
申请者将在我们的硬件部门设计并验证我们下一代高速FPGA/ASIC网络和安全区块，并将参与这些设计方案的设计执行，验证，以及产品化等等一系列工作。
Job Requirements
•Recent or upcoming graduate with strong academic background.
•MS in Electrical Engineering or related, plus 1 year FPGA or ASIC design experience.
•Solid background in FPGA or ASIC design, including RTL coding and synthesis, simulation and timing analysis is required.
•Proficiency in Verilog coding and verification a must. Good scripting skills, such as Perl, TCL are desired.
•Strong written and verbal communication skills. Good English written and reading skill is a plus.
•Must be a team player.
Job Description
Applicant will design and verify high speed networking and security blocks on our next generation FPGA/ASIC in our hardware department. Applicant will be responsible for the implementation, verification, and delivery of these designs.
|
