职位描述：
Responsible for architect, design and implement the FPGA based verification environment for a complex DSP oriented SOC. Partition the design across multiple FPGAs; run logical and physical synthesis. Design and implement the debugging infrastructures to build a useful emulation platform for the system verification engineers.
Requirements:
-?Must be fluent in both Verilog and VHDL, and both RTL (synthesizable) and behavioral SystemC is a plus
- Must have SoC Design or Verification Experience
-?Knowledge of Xilinx Virtex 2 Pro and Virtex 4 a plus
-?Experience using Modelsim, Synplicity and Xilinx ISE Tools
- Experience with the common lab equipments, Logic Analyzer, Oscilloscope, and Signal generator.
- Experience of working DSP algorithm on FPGA is a plus
- Experience of interfacing DSP chip with FPGA is a plus
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