nvidia

信区: Job
标  题: nvidia补充招聘physical Design Engineer
发信站: 日月光华 (2006年12月29日13:58:22 星期五)


Physical design engineer
   LOCATION:  Shanghai, China
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of
Graphics processors, integrated chipsets and other ASICs targeted at the
desktop, laptop, workstation, set-top box and home networking markets.
- Participating in the efforts in establishing CAD and physical design
methodologies, flow automation, chip floorplan, power/clock distribution,
chip assembly and P&R, timing closure, - Static timing analysis, power and
noise analysis and back-end verification across multiple projects.



MINIMUM REQUIREMENTS:
- MSEE or MSCS
- project experience in VLSI physical design implementation on 0.15u,
0.13u, or 90 nanometer technology.
- Understanding of custom Macro blocks such as RAMs, CAMs, high-speed IO
drivers.
- Understanding Timing closure, clock/power Distribution and analysis, RC
Extraction and correlation, place and route and tapeout issues.
- Working knowledge of deep sub-micron routing issues as they relate to
power and timing.
- Circuit level comprehension of time critical paths. Spice experience a
plus.
- Experience with P&R and timing analysis CAD tools from Synopsys
(Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence
(Physical Studio) or Magma.
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred.
- Courses taken in digital design, logic design and verilog synthesis
- Students missed our writing test during NVIDIA campus recruiting.

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