威盛电子（中国）有限公司

【Group./Dept.】Logic

【Responsibilities】
This position is responsible for IC Front-end design flow for design implementation.
The engineer will develop and maintain scripted flows and methodologies to improve
RTL to GDS design productivity in the following areas: logic synthesis/physical synthesis,
DFT, static timing analysis, function verification, power consumption optimization, etc.
Responsibility
1.ASIC design flow and methodology development for RTL-to-GDS implementation
2.New EDA tool evaluation
3.Intenal script development, utilizing Perl, TCL and C-Shell
4.Maintenance and enhancement of internal tools

【Requirements】
1.1. BS degree or above in Electrical Engineering, Computer Science/Engineering, or related engineering fields;
2.Strong Verilog coding experience.
3.Strong verbal communication and interpersonal skills to work closely with a variety of individual contributors and managers; Team work spirit
4.Good spoken and written English skills.
5.The following items are plus :
a)Experienced in commercial EDA tools (e.g., Synopsys, Cadence, Mentor, Magma etc)
b)Experience on RTL design
c)Tcl/TK, C- Shell, Perl, SystemVerilog
d)Technical expertise in one of the following areas are preferred: VLSI technologies, IC design flow, design for manufacturability (DFM)