北京联聘科技公司

JD
1.IP/Module development by Verilog coding and C modeling where necessary,
doing simulations, synthesis, create module block guide and module/chip level verifications.
2.Digital IC designs primarily focused on MCU products, play partial or
full role in SOC design area includes RTL code using Verilog HDL,
functional verification, synthesis, DFT, ATPG, formal verification, Power
analysis, clock & reset strategy, top-level integration and timing closure
3.New design methodology exploring for both SOC projects and IPs
4.Work closely with product engineer to do test patterns
generation/conversion/debugging and deliver final test patterns to product engineer
5.Participate in the system architecture definition and work as a global
team to do complex SOC design based on embedded MCU

Requirement
1.Master and PhD Degree in Electronic, Communication and Microelectronics Engineering.
2.Relevant project experience in digital designs based on high-level languages, either
in ASIC or FPGA, with basic knowledge of digital design flow, including coding, simulation,
synthesis, DFT, STA, test and physical implementation.
3.Relevant experience in the area of embedded processors, MCU is a big plus.
4.Familiar with main EDA tools, such Synopsys, Cadence and Mentor. Good grasp of Verilog/VHDL, C/C++ and Perl/TCL scripts in Linux/Unix environment.(Senior)
5.Good English reading, writing, good verbal English is preferred
6.Strong teamwork sense, good communication skills and strong self-motivation is required（freescale）