- 工作地点：北京
- 职位：ASIC Verification Engineer
- 信息来源：中华英才网
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-Building up verification environment and completing logic verification
-Development of on-chip-bus verification kit for testbench automation (TBA) and assertion based formal verification (ABFV)
-Design IP verification using TBA and ABFV
-Verification methodology development and promotion
Requirement
-Requires MS or above with major in EE/CS related field
-Familiar with SoC verification / IC design flow and Verilog language, experience in SoC design is a plus
-Experience with verification languages such as SystemVerilog, OpenVera, PSL, Specman e language
-Good programming capability in C++
-Familiar with one or more industry simulators: VCS, Incisive, MTI
-Familiar with one or more scripting languages: Tcl, Perl, csh
-Self-motivated and good team player
Location
Beijing
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