冠捷半导体（上海）有限公司

Headquartered in Sunnyvale, California, Silicon Storage Technology, Inc (SST) was founded in 1989 and got listed on the NASDAQ in 1995. SST designs, manufactures and markets a diversified range of memory and non-memory products for high volume applications in the digital consumer, networking, wireless communications and Internet computing markets. SST is a leading provider of nonvolatile memory solutions with product families that include various densities of high functionality flash memory components and flash mass storage products and 8-bit microcontrollers with on-chip flash memory. SST also offers its patented SuperFlash® technology for embedded applications through its world-class manufacturing partners and technology licensees IBM, Motorola, National Semiconductor, NEC Corporation, Oki Electric Industry Co. Ltd., Samsung Electronics Co. Ltd., SANYO Electric Co., Ltd., Seiko Epson Corp.

简历敬请投递至hrchina@

投递时请注意在邮件标题中注明应聘职位及信息来源；请勿多次重复投递；请勿同时投递3个以上职位。谢谢！

Job Description and Responsibilities:

-Contribute to physical layout of various memory chip circuit blocks, responsible for circuit block LVS/DRC verification.

-Contribute to full chip level layout and verification, as well as tapeout process.

-Learning the working knowledge of current CAD tools.

Key Competency Requirements:

-Familiar with using Cadence Design Environment.

-Understanding of basic CMO design and process is a must.

Education Requires:

-BSEE/MSEE or other related engineering degree.

Experience Required:

-Fresh graduate.