- 工作地点：上海
- 职位：
- 信息来源：日月光华
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创锐讯通讯技术(上海)有限公司 复旦大学宣讲会
时间: 11.4 周四下午2:00
地点: 复旦大学微电子楼389室
学校地址: 上海市张衡路825号
公司计划招收IC设计、软件和系统的研发工程师，有兴趣的同学可以去现场咨询及投递
简历，也可将简历寄至: Helen.song@。
ASIC Design Engineer
Education:
. BS in Electrical/Electronics Engineering, MS preferred.
Experience:
. Good communication skills in English.
. Experience in Bluetooth chip design a plus
. Must be proficient in RTL coding, logic synthesis, gate-level simulations.
. Good knowledge of IC design backend flows.
. Experiences in IC life-cycle from conception, design, verification,
top-level netlist with pads to tape-out, chip-testing and mass-production.
. FPGA, PCB or embedded SW skill is a plus.
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
The Digital Design Engineer will be responsible for designing our wireless
and SOC ASIC's. You will work closely with our architecture/algorithm
engineers to explore ideas for next generation products and then develop
RTL to tern these ideas into customer solutions.
. Chip features specification and RTL design
. Synthesis, verification, timing.
. FPGA emulation, lab validation and debugging
Hardware Design Engineer
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
(1)Hardware design for Ethernet communication products.
(2)Board debug and relative EMI, ESD and Surge test.
(3)PCB layout support with layout guide
(4)Chip test and verification.
(4)Co-work with ASIC design team.
(5)AE team support.
EDUCATION:
MS in Electrical/Electronics Engineering or Communication Engineering
EXPERIENCE:
New gratuate: Circuit Schematic, PCB layout design experience or FPGA
experience is a plus
Digital Verification Engineer
Job Overview:
The Digital Verification Engineer will be responsible for the simulation and
verification to craft our wireless and SoC ASICs. This position requires
working with our architecture/algorithm and design engineers to prove
correctness and measure performance of our algorithms and RTL.
Responsibilities include developing simulation environments used by our
test development team to exercise Matlab and Verilog models, as well as
evaluate third party tools and develop methodologies which enhance our
ability to produce high quality ASICs.
Duties/Responsibilities:
. Developing verification environments, and evaluate third party tools and
develop efficient methodologies.
. Develope directed and random cases to verifiy the digital design.
. FPGA emulation, lab validation and debugging.
Qualifications:
. MS in Electrical/Electronics Engineering
. Experience with various verification flows is required. With a proven
track record of delivering successful ASICs is a plus.
. A strong background in software is a must, along with familiarity with
ASIC design flows.
. One or more advantages as following are highly desirable: A strong
background in digital communication, signal processing and networking
protocols; IC DV experiences in wireless communications or audio
processing; Experiences with SoC design based on ARM/MIPS, AMBA and
external interfaces (such as USB, SDIO etc.) development.
. Good communication skills in English.
. Great team work spirit and self motivation
Skills/Experience:
. Strong background in wireless communcations system, and experience
required in C/C++, Verilog, and ASIC verification techniques.
. Must be proficient in one or more major verification languages, such as
Vera, SystemVerilog.
. Experience in the area of automatic code generation is a plus. Perl and
Unix Shell experience is a plus.
. Good knowledge of IC design backend flows.
. FPGA, PCB or embedded SW skill is a plus.
如何写一份简单、直接、高效的求职信？
:download.yingjiesheng.com:
一个今天胜过两个明天。
