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Responsibilities:
Working with project lead to define FEINT flow setting, including synthesis, equivalence check flow. Define frequency target, power strategy and etc.
Regular run FEINT flow, check quality, drive/co-work IP team on issue solving and QoR improvement.
Develop RTL code for SoC top level and make sure functional correct
Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
Support ASIC bring-up.
Requirements:
Familiar with EDA tools such as DC, Formality, PT, CDC/LEDA;
Strong knowledge of electronics fundamentals;
Strong analytical ability and problem solving skills with good team work spirit;